4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
110 typedef int __bitwise pci_power_t;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
123 static inline const char *pci_power_name(pci_power_t state)
125 return pci_power_names[1 + (int) state];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t;
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t;
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
163 typedef unsigned short __bitwise pci_dev_flags_t;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
173 /* Flag for quirk use to store if quirk-specific ACS is enabled */
174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
175 /* Flag to indicate the device uses dma_alias_devfn */
176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
179 /* Do not use bus resets for device */
180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
194 /* These values come from the PCI Express Spec */
195 enum pcie_link_width {
196 PCIE_LNK_WIDTH_RESRV = 0x00,
204 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
207 /* Based on the PCI Hotplug Spec, but some values are made up by us */
209 PCI_SPEED_33MHz = 0x00,
210 PCI_SPEED_66MHz = 0x01,
211 PCI_SPEED_66MHz_PCIX = 0x02,
212 PCI_SPEED_100MHz_PCIX = 0x03,
213 PCI_SPEED_133MHz_PCIX = 0x04,
214 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
215 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
216 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
217 PCI_SPEED_66MHz_PCIX_266 = 0x09,
218 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
219 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
225 PCI_SPEED_66MHz_PCIX_533 = 0x11,
226 PCI_SPEED_100MHz_PCIX_533 = 0x12,
227 PCI_SPEED_133MHz_PCIX_533 = 0x13,
228 PCIE_SPEED_2_5GT = 0x14,
229 PCIE_SPEED_5_0GT = 0x15,
230 PCIE_SPEED_8_0GT = 0x16,
231 PCI_SPEED_UNKNOWN = 0xff,
234 struct pci_cap_saved_data {
241 struct pci_cap_saved_state {
242 struct hlist_node next;
243 struct pci_cap_saved_data cap;
246 struct pcie_link_state;
252 * The pci_dev structure is used to describe PCI devices.
255 struct list_head bus_list; /* node in per-bus list */
256 struct pci_bus *bus; /* bus this device is on */
257 struct pci_bus *subordinate; /* bus this device bridges to */
259 void *sysdata; /* hook for sys-specific extension */
260 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
261 struct pci_slot *slot; /* Physical slot this device is in */
263 unsigned int devfn; /* encoded device & function index */
264 unsigned short vendor;
265 unsigned short device;
266 unsigned short subsystem_vendor;
267 unsigned short subsystem_device;
268 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
269 u8 revision; /* PCI revision, low byte of class word */
270 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
271 u8 pcie_cap; /* PCIe capability offset */
272 u8 msi_cap; /* MSI capability offset */
273 u8 msix_cap; /* MSI-X capability offset */
274 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
275 u8 rom_base_reg; /* which config register controls the ROM */
276 u8 pin; /* which interrupt pin this device uses */
277 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
278 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
280 struct pci_driver *driver; /* which driver has allocated this device */
281 u64 dma_mask; /* Mask of the bits of bus address this
282 device implements. Normally this is
283 0xffffffff. You only need to change
284 this if your device has broken DMA
285 or supports 64-bit transfers. */
287 struct device_dma_parameters dma_parms;
289 pci_power_t current_state; /* Current operating state. In ACPI-speak,
290 this is D0-D3, D0 being fully functional,
292 u8 pm_cap; /* PM capability offset */
293 unsigned int pme_support:5; /* Bitmask of states from which PME#
295 unsigned int pme_interrupt:1;
296 unsigned int pme_poll:1; /* Poll device's PME status bit */
297 unsigned int d1_support:1; /* Low power state D1 is supported */
298 unsigned int d2_support:1; /* Low power state D2 is supported */
299 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
300 unsigned int no_d3cold:1; /* D3cold is forbidden */
301 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
302 unsigned int mmio_always_on:1; /* disallow turning off io/mem
303 decoding during bar sizing */
304 unsigned int wakeup_prepared:1;
305 unsigned int runtime_d3cold:1; /* whether go through runtime
306 D3cold, not set for devices
307 powered on/off by the
308 corresponding bridge */
309 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
310 unsigned int d3_delay; /* D3->D0 transition time in ms */
311 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
313 #ifdef CONFIG_PCIEASPM
314 struct pcie_link_state *link_state; /* ASPM link state */
317 pci_channel_state_t error_state; /* current connectivity state */
318 struct device dev; /* Generic device interface */
320 int cfg_size; /* Size of configuration space */
323 * Instead of touching interrupt line and base address registers
324 * directly, use the values stored here. They might be different!
327 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
329 bool match_driver; /* Skip attaching driver */
330 /* These fields are used by common fixups */
331 unsigned int transparent:1; /* Subtractive decode PCI bridge */
332 unsigned int multifunction:1;/* Part of multi-function device */
333 /* keep track of device state */
334 unsigned int is_added:1;
335 unsigned int is_busmaster:1; /* device is busmaster */
336 unsigned int no_msi:1; /* device may not use msi */
337 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
338 unsigned int block_cfg_access:1; /* config space access is blocked */
339 unsigned int broken_parity_status:1; /* Device generates false positive parity */
340 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
341 unsigned int msi_enabled:1;
342 unsigned int msix_enabled:1;
343 unsigned int ari_enabled:1; /* ARI forwarding */
344 unsigned int is_managed:1;
345 unsigned int needs_freset:1; /* Dev requires fundamental reset */
346 unsigned int state_saved:1;
347 unsigned int is_physfn:1;
348 unsigned int is_virtfn:1;
349 unsigned int reset_fn:1;
350 unsigned int is_hotplug_bridge:1;
351 unsigned int __aer_firmware_first_valid:1;
352 unsigned int __aer_firmware_first:1;
353 unsigned int broken_intx_masking:1;
354 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
355 unsigned int irq_managed:1;
356 pci_dev_flags_t dev_flags;
357 atomic_t enable_cnt; /* pci_enable_device has been called */
359 u32 saved_config_space[16]; /* config space saved at suspend time */
360 struct hlist_head saved_cap_space;
361 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
362 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
363 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
364 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
365 #ifdef CONFIG_PCI_MSI
366 struct list_head msi_list;
367 const struct attribute_group **msi_irq_groups;
370 #ifdef CONFIG_PCI_ATS
372 struct pci_sriov *sriov; /* SR-IOV capability related */
373 struct pci_dev *physfn; /* the PF this VF is associated with */
375 struct pci_ats *ats; /* Address Translation Service */
377 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
378 size_t romlen; /* Length of ROM if it's not from the BAR */
379 char *driver_override; /* Driver name to force a match */
382 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
384 #ifdef CONFIG_PCI_IOV
391 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
393 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
394 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
396 static inline int pci_channel_offline(struct pci_dev *pdev)
398 return (pdev->error_state != pci_channel_io_normal);
401 struct pci_host_bridge {
403 struct pci_bus *bus; /* root bus */
404 struct list_head windows; /* resource_entry */
405 void (*release_fn)(struct pci_host_bridge *);
409 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
410 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
411 void (*release_fn)(struct pci_host_bridge *),
414 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
417 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
418 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
419 * buses below host bridges or subtractive decode bridges) go in the list.
420 * Use pci_bus_for_each_resource() to iterate through all the resources.
424 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
425 * and there's no way to program the bridge with the details of the window.
426 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
427 * decode bit set, because they are explicit and can be programmed with _SRS.
429 #define PCI_SUBTRACTIVE_DECODE 0x1
431 struct pci_bus_resource {
432 struct list_head list;
433 struct resource *res;
437 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
440 struct list_head node; /* node in list of buses */
441 struct pci_bus *parent; /* parent bus this bridge is on */
442 struct list_head children; /* list of child buses */
443 struct list_head devices; /* list of devices on this bus */
444 struct pci_dev *self; /* bridge device as seen by parent */
445 struct list_head slots; /* list of slots on this bus */
446 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
447 struct list_head resources; /* address space routed to this bus */
448 struct resource busn_res; /* bus numbers routed to this bus */
450 struct pci_ops *ops; /* configuration access functions */
451 struct msi_controller *msi; /* MSI controller */
452 void *sysdata; /* hook for sys-specific extension */
453 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
455 unsigned char number; /* bus number */
456 unsigned char primary; /* number of primary bridge */
457 unsigned char max_bus_speed; /* enum pci_bus_speed */
458 unsigned char cur_bus_speed; /* enum pci_bus_speed */
459 #ifdef CONFIG_PCI_DOMAINS_GENERIC
465 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
466 pci_bus_flags_t bus_flags; /* inherited by child buses */
467 struct device *bridge;
469 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
470 struct bin_attribute *legacy_mem; /* legacy mem */
471 unsigned int is_added:1;
474 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
477 * Returns true if the PCI bus is root (behind host-PCI bridge),
480 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
481 * This is incorrect because "virtual" buses added for SR-IOV (via
482 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
484 static inline bool pci_is_root_bus(struct pci_bus *pbus)
486 return !(pbus->parent);
490 * pci_is_bridge - check if the PCI device is a bridge
493 * Return true if the PCI device is bridge whether it has subordinate
496 static inline bool pci_is_bridge(struct pci_dev *dev)
498 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
499 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
502 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
504 dev = pci_physfn(dev);
505 if (pci_is_root_bus(dev->bus))
508 return dev->bus->self;
511 #ifdef CONFIG_PCI_MSI
512 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
514 return pci_dev->msi_enabled || pci_dev->msix_enabled;
517 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
521 * Error values that may be returned by PCI functions.
523 #define PCIBIOS_SUCCESSFUL 0x00
524 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
525 #define PCIBIOS_BAD_VENDOR_ID 0x83
526 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
527 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
528 #define PCIBIOS_SET_FAILED 0x88
529 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
532 * Translate above to generic errno for passing back through non-PCI code.
534 static inline int pcibios_err_to_errno(int err)
536 if (err <= PCIBIOS_SUCCESSFUL)
537 return err; /* Assume already errno */
540 case PCIBIOS_FUNC_NOT_SUPPORTED:
542 case PCIBIOS_BAD_VENDOR_ID:
544 case PCIBIOS_DEVICE_NOT_FOUND:
546 case PCIBIOS_BAD_REGISTER_NUMBER:
548 case PCIBIOS_SET_FAILED:
550 case PCIBIOS_BUFFER_TOO_SMALL:
557 /* Low-level architecture-dependent routines */
560 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
561 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
565 * ACPI needs to be able to access PCI config space before we've done a
566 * PCI bus scan and created pci_bus structures.
568 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
569 int reg, int len, u32 *val);
570 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
571 int reg, int len, u32 val);
573 struct pci_bus_region {
579 spinlock_t lock; /* protects list, index */
580 struct list_head list; /* for IDs added at runtime */
585 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
586 * a set of callbacks in struct pci_error_handlers, that device driver
587 * will be notified of PCI bus errors, and will be driven to recovery
588 * when an error occurs.
591 typedef unsigned int __bitwise pci_ers_result_t;
593 enum pci_ers_result {
594 /* no result/none/not supported in device driver */
595 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
597 /* Device driver can recover without slot reset */
598 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
600 /* Device driver wants slot to be reset. */
601 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
603 /* Device has completely failed, is unrecoverable */
604 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
606 /* Device driver is fully recovered and operational */
607 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
609 /* No AER capabilities registered for the driver */
610 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
613 /* PCI bus error event callbacks */
614 struct pci_error_handlers {
615 /* PCI bus error detected on this device */
616 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
617 enum pci_channel_state error);
619 /* MMIO has been re-enabled, but not DMA */
620 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
622 /* PCI Express link has been reset */
623 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
625 /* PCI slot has been reset */
626 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
628 /* PCI function reset prepare or completed */
629 void (*reset_notify)(struct pci_dev *dev, bool prepare);
631 /* Device driver may resume normal operations */
632 void (*resume)(struct pci_dev *dev);
638 struct list_head node;
640 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
641 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
642 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
643 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
644 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
645 int (*resume_early) (struct pci_dev *dev);
646 int (*resume) (struct pci_dev *dev); /* Device woken up */
647 void (*shutdown) (struct pci_dev *dev);
648 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
649 const struct pci_error_handlers *err_handler;
650 struct device_driver driver;
651 struct pci_dynids dynids;
654 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
657 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
658 * @_table: device table name
660 * This macro is deprecated and should not be used in new code.
662 #define DEFINE_PCI_DEVICE_TABLE(_table) \
663 const struct pci_device_id _table[]
666 * PCI_DEVICE - macro used to describe a specific pci device
667 * @vend: the 16 bit PCI Vendor ID
668 * @dev: the 16 bit PCI Device ID
670 * This macro is used to create a struct pci_device_id that matches a
671 * specific device. The subvendor and subdevice fields will be set to
674 #define PCI_DEVICE(vend,dev) \
675 .vendor = (vend), .device = (dev), \
676 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
679 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
680 * @vend: the 16 bit PCI Vendor ID
681 * @dev: the 16 bit PCI Device ID
682 * @subvend: the 16 bit PCI Subvendor ID
683 * @subdev: the 16 bit PCI Subdevice ID
685 * This macro is used to create a struct pci_device_id that matches a
686 * specific device with subsystem information.
688 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
689 .vendor = (vend), .device = (dev), \
690 .subvendor = (subvend), .subdevice = (subdev)
693 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
694 * @dev_class: the class, subclass, prog-if triple for this device
695 * @dev_class_mask: the class mask for this device
697 * This macro is used to create a struct pci_device_id that matches a
698 * specific PCI class. The vendor, device, subvendor, and subdevice
699 * fields will be set to PCI_ANY_ID.
701 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
702 .class = (dev_class), .class_mask = (dev_class_mask), \
703 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
704 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
707 * PCI_VDEVICE - macro used to describe a specific pci device in short form
708 * @vend: the vendor name
709 * @dev: the 16 bit PCI Device ID
711 * This macro is used to create a struct pci_device_id that matches a
712 * specific PCI device. The subvendor, and subdevice fields will be set
713 * to PCI_ANY_ID. The macro allows the next field to follow as the device
717 #define PCI_VDEVICE(vend, dev) \
718 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
719 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
721 /* these external functions are only available when PCI support is enabled */
724 void pcie_bus_configure_settings(struct pci_bus *bus);
726 enum pcie_bus_config_types {
729 PCIE_BUS_PERFORMANCE,
733 extern enum pcie_bus_config_types pcie_bus_config;
735 extern struct bus_type pci_bus_type;
737 /* Do NOT directly access these two variables, unless you are arch-specific PCI
738 * code, or PCI core code. */
739 extern struct list_head pci_root_buses; /* list of all known PCI buses */
740 /* Some device drivers need know if PCI is initiated */
741 int no_pci_devices(void);
743 void pcibios_resource_survey_bus(struct pci_bus *bus);
744 void pcibios_add_bus(struct pci_bus *bus);
745 void pcibios_remove_bus(struct pci_bus *bus);
746 void pcibios_fixup_bus(struct pci_bus *);
747 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
748 /* Architecture-specific versions may override this (weak) */
749 char *pcibios_setup(char *str);
751 /* Used only when drivers/pci/setup.c is used */
752 resource_size_t pcibios_align_resource(void *, const struct resource *,
755 void pcibios_update_irq(struct pci_dev *, int irq);
757 /* Weak but can be overriden by arch */
758 void pci_fixup_cardbus(struct pci_bus *);
760 /* Generic PCI functions used internally */
762 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
763 struct resource *res);
764 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
765 struct pci_bus_region *region);
766 void pcibios_scan_specific_bus(int busn);
767 struct pci_bus *pci_find_bus(int domain, int busnr);
768 void pci_bus_add_devices(const struct pci_bus *bus);
769 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
770 struct pci_ops *ops, void *sysdata);
771 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
772 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
773 struct pci_ops *ops, void *sysdata,
774 struct list_head *resources);
775 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
776 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
777 void pci_bus_release_busn_res(struct pci_bus *b);
778 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
779 struct pci_ops *ops, void *sysdata,
780 struct list_head *resources);
781 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
783 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
784 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
786 struct hotplug_slot *hotplug);
787 void pci_destroy_slot(struct pci_slot *slot);
788 int pci_scan_slot(struct pci_bus *bus, int devfn);
789 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
790 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
791 unsigned int pci_scan_child_bus(struct pci_bus *bus);
792 void pci_bus_add_device(struct pci_dev *dev);
793 void pci_read_bridge_bases(struct pci_bus *child);
794 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
795 struct resource *res);
796 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
797 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
798 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
799 struct pci_dev *pci_dev_get(struct pci_dev *dev);
800 void pci_dev_put(struct pci_dev *dev);
801 void pci_remove_bus(struct pci_bus *b);
802 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
803 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
804 void pci_stop_root_bus(struct pci_bus *bus);
805 void pci_remove_root_bus(struct pci_bus *bus);
806 void pci_setup_cardbus(struct pci_bus *bus);
807 void pci_sort_breadthfirst(void);
808 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
809 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
810 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
812 /* Generic PCI functions exported to card drivers */
814 enum pci_lost_interrupt_reason {
815 PCI_LOST_IRQ_NO_INFORMATION = 0,
816 PCI_LOST_IRQ_DISABLE_MSI,
817 PCI_LOST_IRQ_DISABLE_MSIX,
818 PCI_LOST_IRQ_DISABLE_ACPI,
820 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
821 int pci_find_capability(struct pci_dev *dev, int cap);
822 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
823 int pci_find_ext_capability(struct pci_dev *dev, int cap);
824 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
825 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
826 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
827 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
829 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
830 struct pci_dev *from);
831 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
832 unsigned int ss_vendor, unsigned int ss_device,
833 struct pci_dev *from);
834 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
835 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
837 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
840 return pci_get_domain_bus_and_slot(0, bus, devfn);
842 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
843 int pci_dev_present(const struct pci_device_id *ids);
845 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
847 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
848 int where, u16 *val);
849 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
850 int where, u32 *val);
851 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
853 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
855 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
857 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
859 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
861 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
863 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
865 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
867 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
870 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
872 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
874 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
876 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
878 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
880 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
883 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
886 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
887 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
888 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
889 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
890 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
892 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
895 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
898 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
901 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
904 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
907 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
910 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
913 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
916 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
919 /* user-space driven config access */
920 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
921 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
922 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
923 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
924 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
925 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
927 int __must_check pci_enable_device(struct pci_dev *dev);
928 int __must_check pci_enable_device_io(struct pci_dev *dev);
929 int __must_check pci_enable_device_mem(struct pci_dev *dev);
930 int __must_check pci_reenable_device(struct pci_dev *);
931 int __must_check pcim_enable_device(struct pci_dev *pdev);
932 void pcim_pin_device(struct pci_dev *pdev);
934 static inline int pci_is_enabled(struct pci_dev *pdev)
936 return (atomic_read(&pdev->enable_cnt) > 0);
939 static inline int pci_is_managed(struct pci_dev *pdev)
941 return pdev->is_managed;
944 void pci_disable_device(struct pci_dev *dev);
946 extern unsigned int pcibios_max_latency;
947 void pci_set_master(struct pci_dev *dev);
948 void pci_clear_master(struct pci_dev *dev);
950 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
951 int pci_set_cacheline_size(struct pci_dev *dev);
952 #define HAVE_PCI_SET_MWI
953 int __must_check pci_set_mwi(struct pci_dev *dev);
954 int pci_try_set_mwi(struct pci_dev *dev);
955 void pci_clear_mwi(struct pci_dev *dev);
956 void pci_intx(struct pci_dev *dev, int enable);
957 bool pci_intx_mask_supported(struct pci_dev *dev);
958 bool pci_check_and_mask_intx(struct pci_dev *dev);
959 bool pci_check_and_unmask_intx(struct pci_dev *dev);
960 void pci_msi_off(struct pci_dev *dev);
961 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
962 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
963 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
964 int pci_wait_for_pending_transaction(struct pci_dev *dev);
965 int pcix_get_max_mmrbc(struct pci_dev *dev);
966 int pcix_get_mmrbc(struct pci_dev *dev);
967 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
968 int pcie_get_readrq(struct pci_dev *dev);
969 int pcie_set_readrq(struct pci_dev *dev, int rq);
970 int pcie_get_mps(struct pci_dev *dev);
971 int pcie_set_mps(struct pci_dev *dev, int mps);
972 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
973 enum pcie_link_width *width);
974 int __pci_reset_function(struct pci_dev *dev);
975 int __pci_reset_function_locked(struct pci_dev *dev);
976 int pci_reset_function(struct pci_dev *dev);
977 int pci_try_reset_function(struct pci_dev *dev);
978 int pci_probe_reset_slot(struct pci_slot *slot);
979 int pci_reset_slot(struct pci_slot *slot);
980 int pci_try_reset_slot(struct pci_slot *slot);
981 int pci_probe_reset_bus(struct pci_bus *bus);
982 int pci_reset_bus(struct pci_bus *bus);
983 int pci_try_reset_bus(struct pci_bus *bus);
984 void pci_reset_secondary_bus(struct pci_dev *dev);
985 void pcibios_reset_secondary_bus(struct pci_dev *dev);
986 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
987 void pci_update_resource(struct pci_dev *dev, int resno);
988 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
989 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
990 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
991 bool pci_device_is_present(struct pci_dev *pdev);
993 /* ROM control related routines */
994 int pci_enable_rom(struct pci_dev *pdev);
995 void pci_disable_rom(struct pci_dev *pdev);
996 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
997 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
998 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
999 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1001 /* Power management related routines */
1002 int pci_save_state(struct pci_dev *dev);
1003 void pci_restore_state(struct pci_dev *dev);
1004 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1005 int pci_load_saved_state(struct pci_dev *dev,
1006 struct pci_saved_state *state);
1007 int pci_load_and_free_saved_state(struct pci_dev *dev,
1008 struct pci_saved_state **state);
1009 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1010 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1012 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1013 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1014 u16 cap, unsigned int size);
1015 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1016 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1017 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1018 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1019 void pci_pme_active(struct pci_dev *dev, bool enable);
1020 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1021 bool runtime, bool enable);
1022 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1023 int pci_prepare_to_sleep(struct pci_dev *dev);
1024 int pci_back_from_sleep(struct pci_dev *dev);
1025 bool pci_dev_run_wake(struct pci_dev *dev);
1026 bool pci_check_pme_status(struct pci_dev *dev);
1027 void pci_pme_wakeup_bus(struct pci_bus *bus);
1029 static inline void pci_ignore_hotplug(struct pci_dev *dev)
1031 dev->ignore_hotplug = 1;
1034 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1037 return __pci_enable_wake(dev, state, false, enable);
1040 /* PCI Virtual Channel */
1041 int pci_save_vc_state(struct pci_dev *dev);
1042 void pci_restore_vc_state(struct pci_dev *dev);
1043 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1045 /* For use by arch with custom probe code */
1046 void set_pcie_port_type(struct pci_dev *pdev);
1047 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1049 /* Functions for PCI Hotplug drivers to use */
1050 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1051 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1052 unsigned int pci_rescan_bus(struct pci_bus *bus);
1053 void pci_lock_rescan_remove(void);
1054 void pci_unlock_rescan_remove(void);
1056 /* Vital product data routines */
1057 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1058 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1060 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1061 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1062 void pci_bus_assign_resources(const struct pci_bus *bus);
1063 void pci_bus_size_bridges(struct pci_bus *bus);
1064 int pci_claim_resource(struct pci_dev *, int);
1065 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1066 void pci_assign_unassigned_resources(void);
1067 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1068 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1069 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1070 void pdev_enable_device(struct pci_dev *);
1071 int pci_enable_resources(struct pci_dev *, int mask);
1072 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1073 int (*)(const struct pci_dev *, u8, u8));
1074 #define HAVE_PCI_REQ_REGIONS 2
1075 int __must_check pci_request_regions(struct pci_dev *, const char *);
1076 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1077 void pci_release_regions(struct pci_dev *);
1078 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1079 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1080 void pci_release_region(struct pci_dev *, int);
1081 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1082 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1083 void pci_release_selected_regions(struct pci_dev *, int);
1085 /* drivers/pci/bus.c */
1086 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1087 void pci_bus_put(struct pci_bus *bus);
1088 void pci_add_resource(struct list_head *resources, struct resource *res);
1089 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1090 resource_size_t offset);
1091 void pci_free_resource_list(struct list_head *resources);
1092 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1093 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1094 void pci_bus_remove_resources(struct pci_bus *bus);
1096 #define pci_bus_for_each_resource(bus, res, i) \
1098 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1101 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1102 struct resource *res, resource_size_t size,
1103 resource_size_t align, resource_size_t min,
1104 unsigned long type_mask,
1105 resource_size_t (*alignf)(void *,
1106 const struct resource *,
1112 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1114 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1116 struct pci_bus_region region;
1118 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1119 return region.start;
1122 /* Proper probing supporting hot-pluggable devices */
1123 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1124 const char *mod_name);
1127 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1129 #define pci_register_driver(driver) \
1130 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1132 void pci_unregister_driver(struct pci_driver *dev);
1135 * module_pci_driver() - Helper macro for registering a PCI driver
1136 * @__pci_driver: pci_driver struct
1138 * Helper macro for PCI drivers which do not do anything special in module
1139 * init/exit. This eliminates a lot of boilerplate. Each module may only
1140 * use this macro once, and calling it replaces module_init() and module_exit()
1142 #define module_pci_driver(__pci_driver) \
1143 module_driver(__pci_driver, pci_register_driver, \
1144 pci_unregister_driver)
1146 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1147 int pci_add_dynid(struct pci_driver *drv,
1148 unsigned int vendor, unsigned int device,
1149 unsigned int subvendor, unsigned int subdevice,
1150 unsigned int class, unsigned int class_mask,
1151 unsigned long driver_data);
1152 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1153 struct pci_dev *dev);
1154 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1157 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1159 int pci_cfg_space_size(struct pci_dev *dev);
1160 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1161 void pci_setup_bridge(struct pci_bus *bus);
1162 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1163 unsigned long type);
1165 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1166 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1168 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1169 unsigned int command_bits, u32 flags);
1170 /* kmem_cache style wrapper around pci_alloc_consistent() */
1172 #include <linux/pci-dma.h>
1173 #include <linux/dmapool.h>
1175 #define pci_pool dma_pool
1176 #define pci_pool_create(name, pdev, size, align, allocation) \
1177 dma_pool_create(name, &pdev->dev, size, align, allocation)
1178 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1179 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1180 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1182 enum pci_dma_burst_strategy {
1183 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1184 strategy_parameter is N/A */
1185 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1187 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1188 strategy_parameter byte boundaries */
1192 u32 vector; /* kernel uses to write allocated vector */
1193 u16 entry; /* driver uses to specify entry, OS writes */
1197 #ifdef CONFIG_PCI_MSI
1198 int pci_msi_vec_count(struct pci_dev *dev);
1199 void pci_msi_shutdown(struct pci_dev *dev);
1200 void pci_disable_msi(struct pci_dev *dev);
1201 int pci_msix_vec_count(struct pci_dev *dev);
1202 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1203 void pci_msix_shutdown(struct pci_dev *dev);
1204 void pci_disable_msix(struct pci_dev *dev);
1205 void pci_restore_msi_state(struct pci_dev *dev);
1206 int pci_msi_enabled(void);
1207 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1208 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1210 int rc = pci_enable_msi_range(dev, nvec, nvec);
1215 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1216 int minvec, int maxvec);
1217 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1218 struct msix_entry *entries, int nvec)
1220 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1226 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1227 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1228 static inline void pci_disable_msi(struct pci_dev *dev) { }
1229 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1230 static inline int pci_enable_msix(struct pci_dev *dev,
1231 struct msix_entry *entries, int nvec)
1233 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1234 static inline void pci_disable_msix(struct pci_dev *dev) { }
1235 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1236 static inline int pci_msi_enabled(void) { return 0; }
1237 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1240 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1242 static inline int pci_enable_msix_range(struct pci_dev *dev,
1243 struct msix_entry *entries, int minvec, int maxvec)
1245 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1246 struct msix_entry *entries, int nvec)
1250 #ifdef CONFIG_PCIEPORTBUS
1251 extern bool pcie_ports_disabled;
1252 extern bool pcie_ports_auto;
1254 #define pcie_ports_disabled true
1255 #define pcie_ports_auto false
1258 #ifdef CONFIG_PCIEASPM
1259 bool pcie_aspm_support_enabled(void);
1261 static inline bool pcie_aspm_support_enabled(void) { return false; }
1264 #ifdef CONFIG_PCIEAER
1265 void pci_no_aer(void);
1266 bool pci_aer_available(void);
1268 static inline void pci_no_aer(void) { }
1269 static inline bool pci_aer_available(void) { return false; }
1272 #ifdef CONFIG_PCIE_ECRC
1273 void pcie_set_ecrc_checking(struct pci_dev *dev);
1274 void pcie_ecrc_get_policy(char *str);
1276 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1277 static inline void pcie_ecrc_get_policy(char *str) { }
1280 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1282 #ifdef CONFIG_HT_IRQ
1283 /* The functions a driver should call */
1284 int ht_create_irq(struct pci_dev *dev, int idx);
1285 void ht_destroy_irq(unsigned int irq);
1286 #endif /* CONFIG_HT_IRQ */
1288 void pci_cfg_access_lock(struct pci_dev *dev);
1289 bool pci_cfg_access_trylock(struct pci_dev *dev);
1290 void pci_cfg_access_unlock(struct pci_dev *dev);
1293 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1294 * a PCI domain is defined to be a set of PCI buses which share
1295 * configuration space.
1297 #ifdef CONFIG_PCI_DOMAINS
1298 extern int pci_domains_supported;
1299 int pci_get_new_domain_nr(void);
1301 enum { pci_domains_supported = 0 };
1302 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1303 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1304 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1305 #endif /* CONFIG_PCI_DOMAINS */
1308 * Generic implementation for PCI domain support. If your
1309 * architecture does not need custom management of PCI
1310 * domains then this implementation will be used
1312 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1313 static inline int pci_domain_nr(struct pci_bus *bus)
1315 return bus->domain_nr;
1317 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1319 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1320 struct device *parent)
1325 /* some architectures require additional setup to direct VGA traffic */
1326 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1327 unsigned int command_bits, u32 flags);
1328 void pci_register_set_vga_state(arch_set_vga_state_t func);
1330 #else /* CONFIG_PCI is not enabled */
1333 * If the system does not have PCI, clearly these return errors. Define
1334 * these as simple inline functions to avoid hair in drivers.
1337 #define _PCI_NOP(o, s, t) \
1338 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1340 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1342 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1343 _PCI_NOP(o, word, u16 x) \
1344 _PCI_NOP(o, dword, u32 x)
1345 _PCI_NOP_ALL(read, *)
1346 _PCI_NOP_ALL(write,)
1348 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1349 unsigned int device,
1350 struct pci_dev *from)
1353 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1354 unsigned int device,
1355 unsigned int ss_vendor,
1356 unsigned int ss_device,
1357 struct pci_dev *from)
1360 static inline struct pci_dev *pci_get_class(unsigned int class,
1361 struct pci_dev *from)
1364 #define pci_dev_present(ids) (0)
1365 #define no_pci_devices() (1)
1366 #define pci_dev_put(dev) do { } while (0)
1368 static inline void pci_set_master(struct pci_dev *dev) { }
1369 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1370 static inline void pci_disable_device(struct pci_dev *dev) { }
1371 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1373 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1375 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1378 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1381 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1383 static inline int __pci_register_driver(struct pci_driver *drv,
1384 struct module *owner)
1386 static inline int pci_register_driver(struct pci_driver *drv)
1388 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1389 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1391 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1394 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1397 /* Power management related routines */
1398 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1399 static inline void pci_restore_state(struct pci_dev *dev) { }
1400 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1402 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1404 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1407 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1411 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1413 static inline void pci_release_regions(struct pci_dev *dev) { }
1415 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1417 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1418 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1420 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1422 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1424 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1427 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1431 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1432 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1433 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1435 #define dev_is_pci(d) (false)
1436 #define dev_is_pf(d) (false)
1437 #define dev_num_vf(d) (0)
1438 #endif /* CONFIG_PCI */
1440 /* Include architecture-dependent settings and functions */
1442 #include <asm/pci.h>
1444 /* these helpers provide future and backwards compatibility
1445 * for accessing popular PCI BAR info */
1446 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1447 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1448 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1449 #define pci_resource_len(dev,bar) \
1450 ((pci_resource_start((dev), (bar)) == 0 && \
1451 pci_resource_end((dev), (bar)) == \
1452 pci_resource_start((dev), (bar))) ? 0 : \
1454 (pci_resource_end((dev), (bar)) - \
1455 pci_resource_start((dev), (bar)) + 1))
1457 /* Similar to the helpers above, these manipulate per-pci_dev
1458 * driver-specific data. They are really just a wrapper around
1459 * the generic device structure functions of these calls.
1461 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1463 return dev_get_drvdata(&pdev->dev);
1466 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1468 dev_set_drvdata(&pdev->dev, data);
1471 /* If you want to know what to call your pci_dev, ask this function.
1472 * Again, it's a wrapper around the generic device.
1474 static inline const char *pci_name(const struct pci_dev *pdev)
1476 return dev_name(&pdev->dev);
1480 /* Some archs don't want to expose struct resource to userland as-is
1481 * in sysfs and /proc
1483 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1484 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1485 const struct resource *rsrc, resource_size_t *start,
1486 resource_size_t *end)
1488 *start = rsrc->start;
1491 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1495 * The world is not perfect and supplies us with broken PCI devices.
1496 * For at least a part of these bugs we need a work-around, so both
1497 * generic (drivers/pci/quirks.c) and per-architecture code can define
1498 * fixup hooks to be called for particular buggy devices.
1502 u16 vendor; /* You can use PCI_ANY_ID here of course */
1503 u16 device; /* You can use PCI_ANY_ID here of course */
1504 u32 class; /* You can use PCI_ANY_ID here too */
1505 unsigned int class_shift; /* should be 0, 8, 16 */
1506 void (*hook)(struct pci_dev *dev);
1509 enum pci_fixup_pass {
1510 pci_fixup_early, /* Before probing BARs */
1511 pci_fixup_header, /* After reading configuration header */
1512 pci_fixup_final, /* Final phase of device fixups */
1513 pci_fixup_enable, /* pci_enable_device() time */
1514 pci_fixup_resume, /* pci_device_resume() */
1515 pci_fixup_suspend, /* pci_device_suspend() */
1516 pci_fixup_resume_early, /* pci_device_resume_early() */
1517 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1520 /* Anonymous variables would be nice... */
1521 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1522 class_shift, hook) \
1523 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1524 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1525 = { vendor, device, class, class_shift, hook };
1527 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1528 class_shift, hook) \
1529 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1530 hook, vendor, device, class, class_shift, hook)
1531 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1532 class_shift, hook) \
1533 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1534 hook, vendor, device, class, class_shift, hook)
1535 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1536 class_shift, hook) \
1537 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1538 hook, vendor, device, class, class_shift, hook)
1539 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1540 class_shift, hook) \
1541 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1542 hook, vendor, device, class, class_shift, hook)
1543 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1544 class_shift, hook) \
1545 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1546 resume##hook, vendor, device, class, \
1548 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1549 class_shift, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1551 resume_early##hook, vendor, device, \
1552 class, class_shift, hook)
1553 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1554 class_shift, hook) \
1555 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1556 suspend##hook, vendor, device, class, \
1558 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1559 class_shift, hook) \
1560 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1561 suspend_late##hook, vendor, device, \
1562 class, class_shift, hook)
1564 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1566 hook, vendor, device, PCI_ANY_ID, 0, hook)
1567 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1568 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1569 hook, vendor, device, PCI_ANY_ID, 0, hook)
1570 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1571 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1572 hook, vendor, device, PCI_ANY_ID, 0, hook)
1573 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1574 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1575 hook, vendor, device, PCI_ANY_ID, 0, hook)
1576 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1577 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1578 resume##hook, vendor, device, \
1579 PCI_ANY_ID, 0, hook)
1580 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1582 resume_early##hook, vendor, device, \
1583 PCI_ANY_ID, 0, hook)
1584 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1586 suspend##hook, vendor, device, \
1587 PCI_ANY_ID, 0, hook)
1588 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1590 suspend_late##hook, vendor, device, \
1591 PCI_ANY_ID, 0, hook)
1593 #ifdef CONFIG_PCI_QUIRKS
1594 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1595 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1596 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1598 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1599 struct pci_dev *dev) { }
1600 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1605 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1608 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1609 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1610 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1611 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1612 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1614 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1616 extern int pci_pci_problems;
1617 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1618 #define PCIPCI_TRITON 2
1619 #define PCIPCI_NATOMA 4
1620 #define PCIPCI_VIAETBF 8
1621 #define PCIPCI_VSFX 16
1622 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1623 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1625 extern unsigned long pci_cardbus_io_size;
1626 extern unsigned long pci_cardbus_mem_size;
1627 extern u8 pci_dfl_cache_line_size;
1628 extern u8 pci_cache_line_size;
1630 extern unsigned long pci_hotplug_io_size;
1631 extern unsigned long pci_hotplug_mem_size;
1633 /* Architecture-specific versions may override these (weak) */
1634 void pcibios_disable_device(struct pci_dev *dev);
1635 void pcibios_set_master(struct pci_dev *dev);
1636 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1637 enum pcie_reset_state state);
1638 int pcibios_add_device(struct pci_dev *dev);
1639 void pcibios_release_device(struct pci_dev *dev);
1640 void pcibios_penalize_isa_irq(int irq, int active);
1642 #ifdef CONFIG_HIBERNATE_CALLBACKS
1643 extern struct dev_pm_ops pcibios_pm_ops;
1646 #ifdef CONFIG_PCI_MMCONFIG
1647 void __init pci_mmcfg_early_init(void);
1648 void __init pci_mmcfg_late_init(void);
1650 static inline void pci_mmcfg_early_init(void) { }
1651 static inline void pci_mmcfg_late_init(void) { }
1654 int pci_ext_cfg_avail(void);
1656 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1658 #ifdef CONFIG_PCI_IOV
1659 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1660 void pci_disable_sriov(struct pci_dev *dev);
1661 int pci_num_vf(struct pci_dev *dev);
1662 int pci_vfs_assigned(struct pci_dev *dev);
1663 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1664 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1666 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1668 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1669 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1670 static inline int pci_vfs_assigned(struct pci_dev *dev)
1672 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1674 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1678 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1679 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1680 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1684 * pci_pcie_cap - get the saved PCIe capability offset
1687 * PCIe capability offset is calculated at PCI device initialization
1688 * time and saved in the data structure. This function returns saved
1689 * PCIe capability offset. Using this instead of pci_find_capability()
1690 * reduces unnecessary search in the PCI configuration space. If you
1691 * need to calculate PCIe capability offset from raw device for some
1692 * reasons, please use pci_find_capability() instead.
1694 static inline int pci_pcie_cap(struct pci_dev *dev)
1696 return dev->pcie_cap;
1700 * pci_is_pcie - check if the PCI device is PCI Express capable
1703 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1705 static inline bool pci_is_pcie(struct pci_dev *dev)
1707 return pci_pcie_cap(dev);
1711 * pcie_caps_reg - get the PCIe Capabilities Register
1714 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1716 return dev->pcie_flags_reg;
1720 * pci_pcie_type - get the PCIe device/port type
1723 static inline int pci_pcie_type(const struct pci_dev *dev)
1725 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1728 void pci_request_acs(void);
1729 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1730 bool pci_acs_path_enabled(struct pci_dev *start,
1731 struct pci_dev *end, u16 acs_flags);
1733 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1734 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1736 /* Large Resource Data Type Tag Item Names */
1737 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1738 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1739 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1741 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1742 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1743 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1745 /* Small Resource Data Type Tag Item Names */
1746 #define PCI_VPD_STIN_END 0x78 /* End */
1748 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1750 #define PCI_VPD_SRDT_TIN_MASK 0x78
1751 #define PCI_VPD_SRDT_LEN_MASK 0x07
1753 #define PCI_VPD_LRDT_TAG_SIZE 3
1754 #define PCI_VPD_SRDT_TAG_SIZE 1
1756 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1758 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1759 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1760 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1761 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1764 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1765 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1767 * Returns the extracted Large Resource Data Type length.
1769 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1771 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1775 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1776 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1778 * Returns the extracted Small Resource Data Type length.
1780 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1782 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1786 * pci_vpd_info_field_size - Extracts the information field length
1787 * @lrdt: Pointer to the beginning of an information field header
1789 * Returns the extracted information field length.
1791 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1793 return info_field[2];
1797 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1798 * @buf: Pointer to buffered vpd data
1799 * @off: The offset into the buffer at which to begin the search
1800 * @len: The length of the vpd buffer
1801 * @rdt: The Resource Data Type to search for
1803 * Returns the index where the Resource Data Type was found or
1804 * -ENOENT otherwise.
1806 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1809 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1810 * @buf: Pointer to buffered vpd data
1811 * @off: The offset into the buffer at which to begin the search
1812 * @len: The length of the buffer area, relative to off, in which to search
1813 * @kw: The keyword to search for
1815 * Returns the index where the information field keyword was found or
1816 * -ENOENT otherwise.
1818 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1819 unsigned int len, const char *kw);
1821 /* PCI <-> OF binding helpers */
1824 void pci_set_of_node(struct pci_dev *dev);
1825 void pci_release_of_node(struct pci_dev *dev);
1826 void pci_set_bus_of_node(struct pci_bus *bus);
1827 void pci_release_bus_of_node(struct pci_bus *bus);
1829 /* Arch may override this (weak) */
1830 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1832 static inline struct device_node *
1833 pci_device_to_OF_node(const struct pci_dev *pdev)
1835 return pdev ? pdev->dev.of_node : NULL;
1838 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1840 return bus ? bus->dev.of_node : NULL;
1843 #else /* CONFIG_OF */
1844 static inline void pci_set_of_node(struct pci_dev *dev) { }
1845 static inline void pci_release_of_node(struct pci_dev *dev) { }
1846 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1847 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1848 #endif /* CONFIG_OF */
1851 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1853 return pdev->dev.archdata.edev;
1857 int pci_for_each_dma_alias(struct pci_dev *pdev,
1858 int (*fn)(struct pci_dev *pdev,
1859 u16 alias, void *data), void *data);
1861 /* helper functions for operation of device flag */
1862 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
1864 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
1866 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
1868 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
1870 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
1872 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
1874 #endif /* LINUX_PCI_H */