1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 4
34 #define RK30_MAX_LAYER_SUPPORT 4
35 #define RK_MAX_FB_SUPPORT 4
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 10
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
58 #define RK_FBIOGET_DMABUF_FD 0x5003
59 #define RK_FBIOSET_DMABUF_FD 0x5004
60 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
61 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
62 #define RK_FBIOSET_OVERLAY_STA 0x5018
63 #define RK_FBIOGET_OVERLAY_STA 0X4619
64 #define RK_FBIOSET_ENABLE 0x5019
65 #define RK_FBIOGET_ENABLE 0x5020
66 #define RK_FBIOSET_CONFIG_DONE 0x4628
67 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
68 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
69 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
70 #define RK_FBIOGET_DSP_ADDR 0x4630
71 #define RK_FBIOGET_LIST_STA 0X4631
72 #define RK_FBIOGET_IOMMU_STA 0x4632
73 #define RK_FBIOSET_CLEAR_FB 0x4633
77 #define RK_LF_STATUS_FC 0xef
78 #define RK_LF_STATUS_FR 0xee
79 #define RK_LF_STATUS_NC 0xfe
80 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
83 /* x y mirror or rotate mode */
85 #define X_MIRROR 1 /* up-down flip*/
86 #define Y_MIRROR 2 /* left-right flip */
87 #define X_Y_MIRROR 3 /* the same as rotate 180 degrees */
88 #define ROTATE_90 4 /* clockwise rotate 90 degrees */
89 #define ROTATE_180 8 /* rotate 180 degrees
90 * It is recommended to use X_Y_MIRROR
91 * rather than ROTATE_180
93 #define ROTATE_270 12 /* clockwise rotate 270 degrees */
97 * pixel align value for gpu,align as 64 bytes in an odd number of times
99 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
100 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
101 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
102 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
103 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
106 //#define USE_ION_MMU 1
107 #if defined(CONFIG_ION_ROCKCHIP)
108 extern struct ion_client *rockchip_ion_client_create(const char * name);
111 extern int rk_fb_poll_prmry_screen_vblank(void);
112 extern u32 rk_fb_get_prmry_screen_ft(void);
113 extern u32 rk_fb_get_prmry_screen_vbt(void);
114 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
115 extern int rk_fb_set_prmry_screen_status(int status);
116 extern bool rk_fb_poll_wait_frame_complete(void);
118 /********************************************************************
119 ** display output interface supported by rockchip lcdc *
120 ********************************************************************/
122 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
123 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
126 #define OUT_CCIR656 6
128 #define OUT_S888DUMY 12
129 #define OUT_RGB_AAA 15
130 #define OUT_P16BPP4 24
131 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
132 #define OUT_D888_P565 0x22
135 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
139 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
140 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
141 HAL_PIXEL_FORMAT_RGB_888 = 3,
142 HAL_PIXEL_FORMAT_RGB_565 = 4,
143 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
144 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
145 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
147 /* 0x8 - 0xFF range unavailable */
152 * This range is reserved for pixel formats that are specific to the HAL
153 * implementation. Implementations can use any value in this range to
154 * communicate video pixel formats between their HAL modules. These formats
155 * must not have an alpha channel. Additionally, an EGLimage created from a
156 * gralloc buffer of one of these formats must be supported for use with the
157 * GL_OES_EGL_image_external OpenGL ES extension.
161 * Android YUV format:
163 * This format is exposed outside of the HAL to software decoders and
164 * applications. EGLImageKHR must support it in conjunction with the
165 * OES_EGL_image_external extension.
167 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
168 * by (W/2) x (H/2) Cr and Cb planes.
170 * This format assumes
173 * - a horizontal stride multiple of 16 pixels
174 * - a vertical stride equal to the height
176 * y_size = stride * height
177 * c_size = ALIGN(stride/2, 16) * height/2
178 * size = y_size + c_size * 2
180 * cb_offset = y_size + c_size
183 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
185 /* Legacy formats (deprecated), used by ImageFormat.java */
186 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
187 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
188 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
189 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
190 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
192 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
193 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
194 HAL_PIXEL_FORMAT_YCrCb_420_SP_10 = 0x24, //YUV444_1obit
196 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
201 //display data format
217 enum fb_win_map_order {
218 FB_DEFAULT_ORDER = 0,
219 FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
220 FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
221 FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
222 FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
223 FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
224 FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
225 FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 = 3210,
247 SCREEN_PREPARE_DDR_CHANGE = 0x0,
248 SCREEN_UNPREPARE_DDR_CHANGE,
252 struct fb_bitfield red;
253 struct fb_bitfield green;
254 struct fb_bitfield blue;
255 struct fb_bitfield transp;
258 struct rk_fb_frame_time {
259 u64 last_framedone_t;
265 wait_queue_head_t wait;
270 struct mutex irq_lock;
271 struct task_struct *thread;
274 struct color_key_cfg {
275 u32 win0_color_key_cfg;
276 u32 win1_color_key_cfg;
277 u32 win2_color_key_cfg;
291 struct rk_disp_pwr_ctr_list {
292 struct list_head list;
293 struct pwr_ctr pwr_ctr;
296 typedef enum _TRSP_MODE {
306 struct rk_lcdc_post_cfg{
313 struct rk_lcdc_win_area{
315 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
316 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
317 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
319 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
321 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
323 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
325 unsigned long smem_start;
326 unsigned long cbr_start; /*Cbr memory start address*/
327 #if defined(CONFIG_ION_ROCKCHIP)
328 struct ion_handle *ion_hdl;
330 struct dma_buf *dma_buf;
345 bool state; /*on or off*/
346 bool last_state; /*on or off*/
348 enum data_format format;
349 int z_order; /*win sel layer*/
364 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
365 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
366 u8 yrgb_hsd_mode;//h scale down mode
367 u8 yrgb_vsu_mode;//v scale up mode
368 u8 yrgb_vsd_mode;//v scale down mode
384 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
385 struct rk_lcdc_post_cfg post_cfg;
388 struct rk_lcdc_driver;
390 struct rk_fb_trsm_ops {
392 int (*disable)(void);
393 int (*dsp_pwr_on) (void);
394 int (*dsp_pwr_off) (void);
397 struct rk_lcdc_drv_ops {
398 int (*open) (struct rk_lcdc_driver * dev_drv, int layer_id, bool open);
399 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
400 int (*init_lcdc) (struct rk_lcdc_driver * dev_drv);
401 int (*ioctl) (struct rk_lcdc_driver * dev_drv, unsigned int cmd,
402 unsigned long arg, int layer_id);
403 int (*suspend) (struct rk_lcdc_driver * dev_drv);
404 int (*resume) (struct rk_lcdc_driver * dev_drv);
405 int (*blank) (struct rk_lcdc_driver * dev_drv, int layer_id,
407 int (*set_par) (struct rk_lcdc_driver * dev_drv, int layer_id);
408 int (*pan_display) (struct rk_lcdc_driver * dev_drv, int layer_id);
409 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
410 int (*lcdc_reg_update) (struct rk_lcdc_driver * dev_drv);
411 ssize_t(*get_disp_info) (struct rk_lcdc_driver * dev_drv, char *buf,
413 int (*load_screen) (struct rk_lcdc_driver * dev_drv, bool initscreen);
414 int (*get_win_state) (struct rk_lcdc_driver * dev_drv, int layer_id);
415 int (*ovl_mgr) (struct rk_lcdc_driver * dev_drv, int swap, bool set); //overlay manager
416 int (*fps_mgr) (struct rk_lcdc_driver * dev_drv, int fps, bool set);
417 int (*fb_get_win_id) (struct rk_lcdc_driver * dev_drv, const char *id); //find layer for fb
418 int (*fb_win_remap) (struct rk_lcdc_driver * dev_drv,
419 enum fb_win_map_order order);
420 int (*set_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
421 int (*read_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
422 int (*lcdc_hdmi_process) (struct rk_lcdc_driver * dev_drv, int mode); //some lcdc need to some process in hdmi mode
423 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
424 int (*poll_vblank) (struct rk_lcdc_driver * dev_drv);
425 int (*lcdc_rst) (struct rk_lcdc_driver * dev_drv);
426 int (*dpi_open) (struct rk_lcdc_driver * dev_drv, bool open);
427 int (*dpi_win_sel) (struct rk_lcdc_driver * dev_drv, int layer_id);
428 int (*dpi_status) (struct rk_lcdc_driver * dev_drv);
429 int (*get_dsp_addr)(struct rk_lcdc_driver * dev_drv,unsigned int *dsp_addr);
430 int (*set_dsp_cabc) (struct rk_lcdc_driver * dev_drv, int mode);
431 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
432 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
433 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
434 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
435 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
436 int (*dump_reg) (struct rk_lcdc_driver * dev_drv);
437 int (*mmu_en) (struct rk_lcdc_driver * dev_drv);
438 int (*cfg_done) (struct rk_lcdc_driver * dev_drv);
441 struct rk_fb_area_par {
443 unsigned long phy_addr;
447 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
449 u32 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
451 u32 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
453 u32 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
458 struct rk_fb_win_par {
459 u8 data_format; /*layer data fmt*/
461 u8 z_order; /*win sel layer*/
462 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
467 struct rk_fb_win_cfg_data {
469 int rel_fence_fd[RK_MAX_BUF_NUM];
470 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
471 struct rk_lcdc_post_cfg post_cfg;
476 struct rk_fb_reg_area_data {
477 struct sync_fence *acq_fence;
478 u8 index_buf; /*judge if the buffer is index*/
479 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
480 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
483 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
485 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
487 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
489 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
491 unsigned long smem_start;
492 unsigned long cbr_start; /*Cbr memory start address*/
494 struct ion_handle *ion_handle;
496 struct dma_buf *dma_buf;
497 struct dma_buf_attachment *attachment;
498 struct sg_table *sg_table;
503 struct rk_fb_reg_win_data {
504 u8 data_format; /*layer data fmt*/
506 u8 z_order; /*win sel layer*/
507 u32 area_num; /*maybe two region have the same dma buff,*/
508 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
514 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
517 struct rk_fb_reg_data {
518 struct list_head list;
522 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
523 struct rk_lcdc_post_cfg post_cfg;
524 //struct sync_fence *acq_fence[RK_MAX_BUF_NUM];
525 //int fence_wait_begin;
528 struct rk_lcdc_driver {
534 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
536 int num_buf; //the num_of buffer
538 int fb_index_base; //the first fb index of the lcdc device
539 struct rk_screen *screen0; //some platform have only one lcdc,but extend
540 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
541 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
549 char mmu_dts_name[40];
551 struct rk_fb_reg_area_data reg_area_data;
552 struct mutex fb_win_id_mutex;
554 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
555 spinlock_t cpl_lock; //lock for completion frame done
557 struct rk_fb_vsync vsync_info;
558 struct rk_fb_frame_time frame_time;
559 int wait_fs; //wait for new frame start in kernel
560 struct sw_sync_timeline *timeline;
564 struct list_head update_regs_list;
565 struct mutex update_regs_list_lock;
566 struct kthread_worker update_regs_worker;
567 struct task_struct *update_regs_thread;
568 struct kthread_work update_regs_work;
569 wait_queue_head_t update_regs_wait;
571 struct mutex output_lock;
572 struct rk29fb_info *screen_ctr_info;
573 struct list_head pwrlist_head;
574 struct rk_lcdc_drv_ops *ops;
575 struct rk_fb_trsm_ops *trsm_ops;
576 #ifdef CONFIG_DRM_ROCKCHIP
577 void (*irq_call_back)(struct rk_lcdc_driver *driver);
582 /*disp_mode: dual display mode
583 * NO_DUAL,no dual display,
584 ONE_DUAL,use one lcdc + rk61x for dual display
585 DUAL,use 2 lcdcs for dual display
586 num_fb: the total number of fb
587 num_lcdc: the total number of lcdc
592 struct rk29fb_info *mach_info;
593 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
596 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
599 #if defined(CONFIG_ION_ROCKCHIP)
600 struct ion_client * ion_client;
606 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
607 extern struct rk_fb_trsm_ops * rk_fb_trsm_ops_get(int type);
608 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
609 struct rk_lcdc_win *win, int id);
610 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
611 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
612 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
613 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
614 extern u32 rk_fb_get_prmry_screen_pixclock(void);
615 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
616 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
617 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
618 extern bool is_prmry_rk_lcdc_registered(void);
619 extern int rk_fb_prase_timing_dt(struct device_node *np,
620 struct rk_screen *screen);
621 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
623 extern int rk_fb_dpi_open(bool open);
624 extern int rk_fb_dpi_layer_sel(int layer_id);
625 extern int rk_fb_dpi_status(void);
627 extern int rk_fb_switch_screen(struct rk_screen * screen, int enable, int lcdc_id);
628 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
629 extern int rkfb_create_sysfs(struct fb_info *fbi);
630 extern char *get_format_string(enum data_format, char *fmt);
631 extern int support_uboot_display(void);
632 extern int rk_fb_calc_fps(struct rk_screen * screen, u32 pixclock);
633 extern int rk_get_real_fps(int time);