1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/display/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/version.h>
35 #define RK30_MAX_LCDC_SUPPORT 2
36 #define RK30_MAX_LAYER_SUPPORT 5
37 #define RK_MAX_FB_SUPPORT 5
38 #define RK_WIN_MAX_AREA 4
39 #define RK_MAX_BUF_NUM 11
41 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
42 #define FB0_IOCTL_SET_PANEL 0x6002
48 #define FB0_IOCTL_SET_BUF 0x6017
49 #define FB0_IOCTL_COPY_CURBUF 0x6018
50 #define FB0_IOCTL_CLOSE_BUF 0x6019
53 #define RK_FBIOGET_PANEL_SIZE 0x5001
54 #define RK_FBIOSET_YUV_ADDR 0x5002
55 #define RK_FBIOGET_SCREEN_STATE 0X4620
56 #define RK_FBIOGET_16OR32 0X4621
57 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
58 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
59 #define RK_FBIOSET_HWC_ADDR 0x4624
61 #define RK_FBIOGET_DMABUF_FD 0x5003
62 #define RK_FBIOSET_DMABUF_FD 0x5004
63 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
64 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
65 #define RK_FBIOSET_OVERLAY_STA 0x5018
66 #define RK_FBIOGET_OVERLAY_STA 0X4619
67 #define RK_FBIOSET_ENABLE 0x5019
68 #define RK_FBIOGET_ENABLE 0x5020
69 #define RK_FBIOSET_CONFIG_DONE 0x4628
70 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
71 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
72 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
73 #define RK_FBIOGET_DSP_ADDR 0x4630
74 #define RK_FBIOGET_LIST_STA 0X4631
75 #define RK_FBIOGET_IOMMU_STA 0x4632
76 #define RK_FBIOSET_CLEAR_FB 0x4633
80 #define RK_LF_STATUS_FC 0xef
81 #define RK_LF_STATUS_FR 0xee
82 #define RK_LF_STATUS_NC 0xfe
83 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
86 * pixel align value for gpu,align as 64 bytes in an odd number of times
88 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
89 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
90 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
91 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
92 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
94 #define DUMP_FRAME_NUM 3
96 //#define USE_ION_MMU 1
97 #if defined(CONFIG_ION_ROCKCHIP)
98 extern struct ion_client *rockchip_ion_client_create(const char *name);
101 extern int rk_fb_poll_prmry_screen_vblank(void);
102 extern u32 rk_fb_get_prmry_screen_ft(void);
103 extern u32 rk_fb_get_prmry_screen_vbt(void);
104 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
105 extern int rk_fb_set_prmry_screen_status(int status);
106 extern bool rk_fb_poll_wait_frame_complete(void);
114 #define CSC_MASK (0x3 << CSC_SHIFT)
115 #define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT)
117 #define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK))
118 #define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK))
119 #define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK))
122 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
125 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
126 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
127 HAL_PIXEL_FORMAT_RGB_888 = 3,
128 HAL_PIXEL_FORMAT_RGB_565 = 4,
129 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
130 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
131 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
133 /* 0x8 - 0xFF range unavailable */
138 * This range is reserved for pixel formats that are specific to the HAL
139 * implementation. Implementations can use any value in this range to
140 * communicate video pixel formats between their HAL modules. These formats
141 * must not have an alpha channel. Additionally, an EGLimage created from a
142 * gralloc buffer of one of these formats must be supported for use with the
143 * GL_OES_EGL_image_external OpenGL ES extension.
147 * Android YUV format:
149 * This format is exposed outside of the HAL to software decoders and
150 * applications. EGLImageKHR must support it in conjunction with the
151 * OES_EGL_image_external extension.
153 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
154 * by (W/2) x (H/2) Cr and Cb planes.
156 * This format assumes
159 * - a horizontal stride multiple of 16 pixels
160 * - a vertical stride equal to the height
162 * y_size = stride * height
163 * c_size = ALIGN(stride/2, 16) * height/2
164 * size = y_size + c_size * 2
166 * cb_offset = y_size + c_size
169 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
171 /* Legacy formats (deprecated), used by ImageFormat.java */
174 * YCbCr format default is BT601.
176 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
177 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
178 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
179 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
180 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
182 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
183 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
184 HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit
186 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
187 HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26,
188 HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/
189 HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/
190 HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/
191 HAL_PIXEL_FORMAT_BGRX_8888 = 0x30,
192 HAL_PIXEL_FORMAT_BGR_888 = 0x31,
193 HAL_PIXEL_FORMAT_BGR_565 = 0x32,
195 HAL_PIXEL_FORMAT_YUYV422 = 0x33,
196 HAL_PIXEL_FORMAT_YUYV420 = 0x34,
197 HAL_PIXEL_FORMAT_UYVY422 = 0x35,
198 HAL_PIXEL_FORMAT_UYVY420 = 0x36,
200 HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 =
201 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12),
202 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 =
203 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO),
204 HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 =
205 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP),
206 HAL_PIXEL_FORMAT_YCrCb_444_BT709 =
207 BT709(HAL_PIXEL_FORMAT_YCrCb_444),
209 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 =
210 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
211 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 =
212 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
213 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 =
214 BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
216 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 =
217 BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
218 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 =
219 BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
220 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 =
221 BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
224 //display data format
250 #define IS_YUV_FMT(fmt) ((fmt >= YUV420) ? 1 : 0)
251 #define IS_RGB_FMT(fmt) ((fmt < YUV420) ? 1 : 0)
252 #define IS_FBDC_FMT(fmt) \
253 (((fmt >= FBDC_RGB_565) && (fmt <= FBDC_ABGR_888)) ? 1 : 0)
274 SCREEN_PREPARE_DDR_CHANGE = 0x0,
275 SCREEN_UNPREPARE_DDR_CHANGE,
279 GET_PAGE_FAULT = 0x0,
280 CLR_PAGE_FAULT = 0x1,
281 UNMASK_PAGE_FAULT = 0x2
284 enum rk_vop_feature {
285 SUPPORT_VOP_IDENTIFY = BIT(0),
286 SUPPORT_IFBDC = BIT(1),
287 SUPPORT_AFBDC = BIT(2),
288 SUPPORT_WRITE_BACK = BIT(3),
289 SUPPORT_YUV420_OUTPUT = BIT(4)
292 struct rk_vop_property {
298 enum rk_win_feature {
299 SUPPORT_WIN_IDENTIFY = BIT(0),
300 SUPPORT_SCALE = BIT(1),
301 SUPPORT_YUV = BIT(2),
302 SUPPORT_YUV10BIT = BIT(3),
303 SUPPORT_MULTI_AREA = BIT(4),
304 SUPPORT_HWC_LAYER = BIT(5)
307 struct rk_win_property {
314 struct fb_bitfield red;
315 struct fb_bitfield green;
316 struct fb_bitfield blue;
317 struct fb_bitfield transp;
320 struct rk_fb_frame_time {
321 u64 last_framedone_t;
327 wait_queue_head_t wait;
332 struct mutex irq_lock;
333 struct task_struct *thread;
336 struct color_key_cfg {
337 u32 win0_color_key_cfg;
338 u32 win1_color_key_cfg;
339 u32 win2_color_key_cfg;
348 const char *rgl_name;
353 struct rk_disp_pwr_ctr_list {
354 struct list_head list;
355 struct pwr_ctr pwr_ctr;
358 typedef enum _TRSP_MODE {
368 struct rk_lcdc_post_cfg {
375 struct rk_fb_wb_cfg {
385 struct rk_lcdc_bcsh {
394 struct rk_lcdc_win_area {
396 enum data_format format;
401 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
402 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
403 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
405 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
407 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
409 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
411 u16 xoff; /*mem offset*/
413 unsigned long smem_start;
414 unsigned long cbr_start; /*Cbr memory start address*/
415 #if defined(CONFIG_ION_ROCKCHIP)
416 struct ion_handle *ion_hdl;
418 struct dma_buf *dma_buf;
430 u8 fbdc_dsp_width_ratio;
432 u16 fbdc_mb_vir_width;
433 u16 fbdc_mb_vir_height;
439 u16 fbdc_cmp_index_init;
446 struct rk_win_property property;
447 bool state; /*on or off*/
448 bool last_state; /*on or off*/
450 int z_order; /*win sel layer*/
464 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
465 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
466 u8 yrgb_hsd_mode;//h scale down mode
467 u8 yrgb_vsu_mode;//v scale up mode
468 u8 yrgb_vsd_mode;//v scale down mode
487 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
488 struct rk_lcdc_post_cfg post_cfg;
491 struct rk_lcdc_driver;
493 struct rk_fb_trsm_ops {
495 int (*disable)(void);
496 int (*dsp_pwr_on) (void);
497 int (*dsp_pwr_off) (void);
500 struct rk_lcdc_drv_ops {
501 int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
502 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
503 int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
504 int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
505 unsigned long arg, int layer_id);
506 int (*suspend) (struct rk_lcdc_driver *dev_drv);
507 int (*resume) (struct rk_lcdc_driver *dev_drv);
508 int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
510 int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
511 int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
512 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
513 int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
514 ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
516 int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
517 int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv,
518 u16 *xact, u16 *yact, int *format,
519 u32 *dsp_addr, int *ymirror);
520 int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
521 int format, u16 xact, u16 yact, u16 xvir,
524 int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id);
525 int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
526 int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
527 int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
528 int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
529 u16 fb_win_map_order);
530 int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
531 int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut);
532 int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
533 int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
534 int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
535 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
536 int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
537 int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
538 int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
539 int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
540 int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
541 int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]);
542 int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global);
543 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
544 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
545 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
546 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
547 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
548 int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
549 int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
550 int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
551 int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
552 int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
553 struct overscan *overscan);
554 int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
555 int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable);
556 int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support);
557 int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd);
558 int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable);
559 int (*set_wb)(struct rk_lcdc_driver *dev_drv);
562 struct rk_fb_area_par {
563 u8 data_format; /*layer data fmt*/
569 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
571 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
573 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
575 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
585 struct rk_fb_win_par {
587 u8 z_order; /*win sel layer*/
591 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
595 struct rk_fb_win_cfg_data {
598 short rel_fence_fd[RK_MAX_BUF_NUM];
599 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
600 struct rk_fb_wb_cfg wb_cfg;
603 struct rk_fb_reg_wb_data {
606 struct ion_handle *ion_handle;
607 unsigned long smem_start;
608 unsigned long cbr_start; /*Cbr memory start address*/
613 struct rk_fb_reg_area_data {
614 struct sync_fence *acq_fence;
615 u8 data_format; /*layer data fmt*/
616 u8 index_buf; /*judge if the buffer is index*/
617 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
618 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
622 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
624 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
626 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
628 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
630 u16 xoff; /*mem offset*/
632 unsigned long smem_start;
633 unsigned long cbr_start; /*Cbr memory start address*/
635 struct ion_handle *ion_handle;
637 struct dma_buf *dma_buf;
638 struct dma_buf_attachment *attachment;
639 struct sg_table *sg_table;
647 struct rk_fb_reg_win_data {
649 int z_order; /*win sel layer*/
650 u32 area_num; /*maybe two region have the same dma buff,*/
651 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
658 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
661 struct rk_fb_reg_data {
662 struct list_head list;
666 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
667 struct rk_fb_reg_wb_data reg_wb_data;
670 struct rk_lcdc_driver {
676 struct rk_vop_property property;
678 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
679 struct rk_fb_reg_wb_data wb_data;
681 int num_buf; //the num_of buffer
683 int fb_index_base; //the first fb index of the lcdc device
684 struct rk_screen *screen0; //some platform have only one lcdc,but extend
685 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
686 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
700 char mmu_dts_name[40];
701 struct device *mmu_dev;
704 struct rk_fb_reg_area_data reg_area_data;
706 * front_regs means this config is scaning on the devices.
708 struct rk_fb_reg_data *front_regs;
709 struct mutex front_lock;
711 struct mutex fb_win_id_mutex;
712 struct mutex win_config;
714 struct mutex switch_screen; /*for switch screen*/
715 struct completion frame_done; /*sync for pan_display,whe we set a new
716 frame address to lcdc register,we must
717 make sure the frame begain to display*/
718 spinlock_t cpl_lock; /*lock for completion frame done */
720 struct rk_fb_vsync vsync_info;
721 struct rk_fb_frame_time frame_time;
722 int wait_fs; /*wait for new frame start in kernel */
723 struct sw_sync_timeline *timeline;
727 struct list_head update_regs_list;
728 struct list_head saved_list;
729 struct mutex update_regs_list_lock;
730 struct kthread_worker update_regs_worker;
731 struct task_struct *update_regs_thread;
732 struct kthread_work update_regs_work;
733 wait_queue_head_t update_regs_wait;
735 struct mutex output_lock;
736 struct rk29fb_info *screen_ctr_info;
737 struct list_head pwrlist_head;
738 struct rk_lcdc_drv_ops *ops;
739 struct rk_fb_trsm_ops *trsm_ops;
740 #ifdef CONFIG_DRM_ROCKCHIP
741 void (*irq_call_back)(struct rk_lcdc_driver *driver);
743 struct overscan overscan;
744 struct rk_lcdc_bcsh bcsh;
747 int bcsh_init_status;
750 /*1:hdmi switch uncomplete,0:complete*/
753 struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM];
754 struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM];
755 unsigned int area_support[RK30_MAX_LAYER_SUPPORT];
762 unsigned long fb_phy_base; /* Start of fb address (physical address) */
763 char __iomem *fb_virt_base; /* Start of fb address (virt address) */
765 struct rk_lcdc_driver *lcdc_drv;
767 #if defined(CONFIG_ION_ROCKCHIP)
768 struct ion_handle *ion_hdl;
773 /*disp_mode: dual display mode
774 * NO_DUAL,no dual display,
775 ONE_DUAL,use one lcdc + rk61x for dual display
776 DUAL,use 2 lcdcs for dual display
777 num_fb: the total number of fb
778 num_lcdc: the total number of lcdc
784 struct rk29fb_info *mach_info;
785 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
787 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
790 #if defined(CONFIG_ION_ROCKCHIP)
791 struct ion_client *ion_client;
795 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
796 extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
797 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
798 struct rk_lcdc_win *win, int id);
799 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
800 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
801 extern int rk_fb_get_extern_screen(struct rk_screen *screen);
802 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
803 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
804 extern u32 rk_fb_get_prmry_screen_pixclock(void);
805 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
806 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
807 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
808 extern bool is_prmry_rk_lcdc_registered(void);
809 extern int rk_fb_prase_timing_dt(struct device_node *np,
810 struct rk_screen *screen);
811 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
813 extern int rk_fb_dpi_open(bool open);
814 extern int rk_fb_dpi_layer_sel(int layer_id);
815 extern int rk_fb_dpi_status(void);
817 extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
818 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
819 extern int rkfb_create_sysfs(struct fb_info *fbi);
820 extern char *get_format_string(enum data_format, char *fmt);
821 extern int support_uboot_display(void);
822 extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
823 extern int rk_get_real_fps(int time);
824 extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
825 extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
827 int rk_fb_get_display_policy(void);
828 int rk_fb_pixel_width(int data_format);
829 void trace_buffer_dump(struct device *dev,
830 struct rk_lcdc_driver *dev_drv);
831 extern int rockchip_get_screen_type(void);