1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 4
34 #define RK30_MAX_LAYER_SUPPORT 4
35 #define RK_MAX_FB_SUPPORT 4
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 10
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
58 #define RK_FBIOGET_DMABUF_FD 0x5003
59 #define RK_FBIOSET_DMABUF_FD 0x5004
60 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
61 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
62 #define RK_FBIOSET_OVERLAY_STATE 0x5018
63 #define RK_FBIOGET_OVERLAY_STATE 0X4619
64 #define RK_FBIOSET_ENABLE 0x5019
65 #define RK_FBIOGET_ENABLE 0x5020
66 #define RK_FBIOSET_CONFIG_DONE 0x4628
67 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
68 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
69 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
70 #define RK_FBIOGET_DSP_ADDR 0x4630
71 #define RK_FBIOGET_LIST_STAT 0X4631
75 #define RK_LF_STATUS_FC 0xef
76 #define RK_LF_STATUS_FR 0xee
77 #define RK_LF_STATUS_NC 0xfe
78 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
87 /*#define USE_ION_MMU 1*/
88 #if defined(CONFIG_ION_ROCKCHIP)
89 extern struct ion_client *rockchip_ion_client_create(const char * name);
92 extern int rk_fb_poll_prmry_screen_vblank(void);
93 extern int rk_fb_get_prmry_screen_ft(void);
94 extern bool rk_fb_poll_wait_frame_complete(void);
96 /********************************************************************
97 ** display output interface supported by rockchip lcdc *
98 ********************************************************************/
100 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
101 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
104 #define OUT_CCIR656 6
106 #define OUT_S888DUMY 12
107 #define OUT_RGB_AAA 15
108 #define OUT_P16BPP4 24
109 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
110 #define OUT_D888_P565 0x22
113 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
117 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
118 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
119 HAL_PIXEL_FORMAT_RGB_888 = 3,
120 HAL_PIXEL_FORMAT_RGB_565 = 4,
121 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
122 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
123 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
125 /* 0x8 - 0xFF range unavailable */
130 * This range is reserved for pixel formats that are specific to the HAL
131 * implementation. Implementations can use any value in this range to
132 * communicate video pixel formats between their HAL modules. These formats
133 * must not have an alpha channel. Additionally, an EGLimage created from a
134 * gralloc buffer of one of these formats must be supported for use with the
135 * GL_OES_EGL_image_external OpenGL ES extension.
139 * Android YUV format:
141 * This format is exposed outside of the HAL to software decoders and
142 * applications. EGLImageKHR must support it in conjunction with the
143 * OES_EGL_image_external extension.
145 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
146 * by (W/2) x (H/2) Cr and Cb planes.
148 * This format assumes
151 * - a horizontal stride multiple of 16 pixels
152 * - a vertical stride equal to the height
154 * y_size = stride * height
155 * c_size = ALIGN(stride/2, 16) * height/2
156 * size = y_size + c_size * 2
158 * cb_offset = y_size + c_size
161 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
163 /* Legacy formats (deprecated), used by ImageFormat.java */
164 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
165 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
166 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
167 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
168 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
169 HAL_PIXEL_FORMAT_YCrCb_444 = 0x22, //yuv444
170 HAL_PIXEL_FORMAT_H265 = 0x23, //yuv444
174 //display data format
187 enum fb_win_map_order {
188 FB_DEFAULT_ORDER = 0,
189 FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
190 FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
191 FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
192 FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
193 FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
194 FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
195 FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 = 3210,
207 struct fb_bitfield red;
208 struct fb_bitfield green;
209 struct fb_bitfield blue;
210 struct fb_bitfield transp;
214 wait_queue_head_t wait;
219 struct mutex irq_lock;
220 struct task_struct *thread;
223 struct color_key_cfg {
224 u32 win0_color_key_cfg;
225 u32 win1_color_key_cfg;
226 u32 win2_color_key_cfg;
240 struct rk_disp_pwr_ctr_list {
241 struct list_head list;
242 struct pwr_ctr pwr_ctr;
245 typedef enum _TRSP_MODE {
255 struct rk_lcdc_post_cfg{
262 struct rk_lcdc_win_area{
264 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
265 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
266 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
268 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
270 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
272 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
274 unsigned long smem_start;
275 unsigned long cbr_start; /*Cbr memory start address*/
276 #if defined(CONFIG_ION_ROCKCHIP)
277 struct ion_handle *ion_hdl;
293 bool state; /*on or off*/
295 enum data_format format;
296 u8 z_order; /*win sel layer*/
311 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
312 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
313 u8 yrgb_hsd_mode;//h scale down mode
314 u8 yrgb_vsu_mode;//v scale up mode
315 u8 yrgb_vsd_mode;//v scale down mode
331 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
332 struct rk_lcdc_post_cfg post_cfg;
335 struct rk_lcdc_driver;
337 struct rk_fb_trsm_ops {
339 int (*disable)(void);
342 struct rk_lcdc_drv_ops {
343 int (*open) (struct rk_lcdc_driver * dev_drv, int layer_id, bool open);
344 int (*init_lcdc) (struct rk_lcdc_driver * dev_drv);
345 int (*ioctl) (struct rk_lcdc_driver * dev_drv, unsigned int cmd,
346 unsigned long arg, int layer_id);
347 int (*suspend) (struct rk_lcdc_driver * dev_drv);
348 int (*resume) (struct rk_lcdc_driver * dev_drv);
349 int (*blank) (struct rk_lcdc_driver * dev_drv, int layer_id,
351 int (*set_par) (struct rk_lcdc_driver * dev_drv, int layer_id);
352 int (*pan_display) (struct rk_lcdc_driver * dev_drv, int layer_id);
353 int (*lcdc_reg_update) (struct rk_lcdc_driver * dev_drv);
354 ssize_t(*get_disp_info) (struct rk_lcdc_driver * dev_drv, char *buf,
356 int (*load_screen) (struct rk_lcdc_driver * dev_drv, bool initscreen);
357 int (*get_win_state) (struct rk_lcdc_driver * dev_drv, int layer_id);
358 int (*ovl_mgr) (struct rk_lcdc_driver * dev_drv, int swap, bool set); //overlay manager
359 int (*fps_mgr) (struct rk_lcdc_driver * dev_drv, int fps, bool set);
360 int (*fb_get_win_id) (struct rk_lcdc_driver * dev_drv, const char *id); //find layer for fb
361 int (*fb_win_remap) (struct rk_lcdc_driver * dev_drv,
362 enum fb_win_map_order order);
363 int (*set_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
364 int (*read_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
365 int (*lcdc_hdmi_process) (struct rk_lcdc_driver * dev_drv, int mode); //some lcdc need to some process in hdmi mode
366 int (*poll_vblank) (struct rk_lcdc_driver * dev_drv);
367 int (*lcdc_rst) (struct rk_lcdc_driver * dev_drv);
368 int (*dpi_open) (struct rk_lcdc_driver * dev_drv, bool open);
369 int (*dpi_win_sel) (struct rk_lcdc_driver * dev_drv, int layer_id);
370 int (*dpi_status) (struct rk_lcdc_driver * dev_drv);
371 int (*get_dsp_addr)(struct rk_lcdc_driver * dev_drv,unsigned int *dsp_addr);
372 int (*set_dsp_cabc) (struct rk_lcdc_driver * dev_drv, int mode);
373 int (*set_dsp_hue) (struct rk_lcdc_driver *dev_drv,int hue);
374 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,int bri,int con,int sat);
375 int (*dump_reg) (struct rk_lcdc_driver * dev_drv);
376 int (*mmu_en) (struct rk_lcdc_driver * dev_drv,bool en);
377 int (*cfg_done) (struct rk_lcdc_driver * dev_drv);
380 struct rk_fb_area_par {
382 unsigned long phy_addr;
386 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
388 u32 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
390 u32 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
392 u32 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
397 struct rk_fb_win_par {
398 u8 data_format; /*layer data fmt*/
400 u8 z_order; /*win sel layer*/
401 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
406 struct rk_fb_win_cfg_data {
408 u16 rel_fence_fd[RK_MAX_BUF_NUM];
409 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
410 struct rk_lcdc_post_cfg post_cfg;
415 struct rk_fb_reg_area_data {
416 struct sync_fence *acq_fence;
417 u8 index_buf; /*judge if the buffer is index*/
418 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
419 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
422 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
424 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
426 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
428 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
430 unsigned long smem_start;
431 unsigned long cbr_start; /*Cbr memory start address*/
433 struct ion_handle *ion_handle;
435 struct dma_buf *dma_buf;
436 struct dma_buf_attachment *attachment;
437 struct sg_table *sg_table;
442 struct rk_fb_reg_win_data {
443 u8 data_format; /*layer data fmt*/
445 u8 z_order; /*win sel layer*/
446 u32 area_num; /*maybe two region have the same dma buff,*/
447 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
453 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
456 struct rk_fb_reg_data {
457 struct list_head list;
461 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
462 struct rk_lcdc_post_cfg post_cfg;
463 //struct sync_fence *acq_fence[RK_MAX_BUF_NUM];
464 //int fence_wait_begin;
467 struct rk_lcdc_driver {
473 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
475 int num_buf; //the num_of buffer
477 int fb_index_base; //the first fb index of the lcdc device
478 struct rk_screen *screen0; //some platform have only one lcdc,but extend
479 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
480 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
487 char mmu_dts_name[40];
488 struct rk_fb_reg_area_data reg_area_data;
489 struct mutex fb_win_id_mutex;
491 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
492 spinlock_t cpl_lock; //lock for completion frame done
494 struct rk_fb_vsync vsync_info;
495 int wait_fs; //wait for new frame start in kernel
496 struct sw_sync_timeline *timeline;
499 struct list_head update_regs_list;
500 struct mutex update_regs_list_lock;
501 struct kthread_worker update_regs_worker;
502 struct task_struct *update_regs_thread;
503 struct kthread_work update_regs_work;
505 struct mutex output_lock;
506 struct rk29fb_info *screen_ctr_info;
507 struct list_head pwrlist_head;
508 struct rk_lcdc_drv_ops *ops;
509 struct rk_fb_trsm_ops *trsm_ops;
513 /*disp_mode: dual display mode
514 * NO_DUAL,no dual display,
515 ONE_DUAL,use one lcdc + rk61x for dual display
516 DUAL,use 2 lcdcs for dual display
517 num_fb: the total number of fb
518 num_lcdc: the total number of lcdc
523 struct rk29fb_info *mach_info;
524 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
527 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
530 #if defined(CONFIG_ION_ROCKCHIP)
531 struct ion_client * ion_client;
537 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
538 extern struct rk_fb_trsm_ops * rk_fb_trsm_ops_get(int type);
539 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
540 struct rk_lcdc_win *win, int id);
541 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
542 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
543 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
544 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
545 extern u32 rk_fb_get_prmry_screen_pixclock(void);
546 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
547 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
548 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
549 extern bool is_prmry_rk_lcdc_registered(void);
550 extern int rk_fb_prase_timing_dt(struct device_node *np,
551 struct rk_screen *screen);
552 #ifdef CONFIG_RK_FPGA
553 static int inline support_uboot_display(void)
558 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
560 extern int rk_fb_dpi_open(bool open);
561 extern int rk_fb_dpi_layer_sel(int layer_id);
562 extern int rk_fb_dpi_status(void);
564 extern int rk_fb_switch_screen(struct rk_screen * screen, int enable, int lcdc_id);
565 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
566 extern int rkfb_create_sysfs(struct fb_info *fbi);
567 extern char *get_format_string(enum data_format, char *fmt);
568 extern int support_uboot_display(void);
569 extern int rk_fb_calc_fps(struct rk_screen * screen, u32 pixclock);