1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/display/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 2
34 #define RK30_MAX_LAYER_SUPPORT 5
35 #define RK_MAX_FB_SUPPORT 5
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 11
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
57 #define RK_FBIOSET_HWC_ADDR 0x4624
59 #define RK_FBIOGET_DMABUF_FD 0x5003
60 #define RK_FBIOSET_DMABUF_FD 0x5004
61 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
62 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
63 #define RK_FBIOSET_OVERLAY_STA 0x5018
64 #define RK_FBIOGET_OVERLAY_STA 0X4619
65 #define RK_FBIOSET_ENABLE 0x5019
66 #define RK_FBIOGET_ENABLE 0x5020
67 #define RK_FBIOSET_CONFIG_DONE 0x4628
68 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
69 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
70 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
71 #define RK_FBIOGET_DSP_ADDR 0x4630
72 #define RK_FBIOGET_LIST_STA 0X4631
73 #define RK_FBIOGET_IOMMU_STA 0x4632
74 #define RK_FBIOSET_CLEAR_FB 0x4633
78 #define RK_LF_STATUS_FC 0xef
79 #define RK_LF_STATUS_FR 0xee
80 #define RK_LF_STATUS_NC 0xfe
81 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
84 * pixel align value for gpu,align as 64 bytes in an odd number of times
86 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
87 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
88 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
89 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
90 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
92 #define DUMP_FRAME_NUM 3
94 //#define USE_ION_MMU 1
95 #if defined(CONFIG_ION_ROCKCHIP)
96 extern struct ion_client *rockchip_ion_client_create(const char *name);
99 extern int rk_fb_poll_prmry_screen_vblank(void);
100 extern u32 rk_fb_get_prmry_screen_ft(void);
101 extern u32 rk_fb_get_prmry_screen_vbt(void);
102 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
103 extern int rk_fb_set_prmry_screen_status(int status);
104 extern bool rk_fb_poll_wait_frame_complete(void);
112 #define CSC_MASK (0x3 << CSC_SHIFT)
113 #define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT)
115 #define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK))
116 #define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK))
117 #define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK))
120 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
123 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
124 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
125 HAL_PIXEL_FORMAT_RGB_888 = 3,
126 HAL_PIXEL_FORMAT_RGB_565 = 4,
127 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
128 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
129 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
131 /* 0x8 - 0xFF range unavailable */
136 * This range is reserved for pixel formats that are specific to the HAL
137 * implementation. Implementations can use any value in this range to
138 * communicate video pixel formats between their HAL modules. These formats
139 * must not have an alpha channel. Additionally, an EGLimage created from a
140 * gralloc buffer of one of these formats must be supported for use with the
141 * GL_OES_EGL_image_external OpenGL ES extension.
145 * Android YUV format:
147 * This format is exposed outside of the HAL to software decoders and
148 * applications. EGLImageKHR must support it in conjunction with the
149 * OES_EGL_image_external extension.
151 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
152 * by (W/2) x (H/2) Cr and Cb planes.
154 * This format assumes
157 * - a horizontal stride multiple of 16 pixels
158 * - a vertical stride equal to the height
160 * y_size = stride * height
161 * c_size = ALIGN(stride/2, 16) * height/2
162 * size = y_size + c_size * 2
164 * cb_offset = y_size + c_size
167 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
169 /* Legacy formats (deprecated), used by ImageFormat.java */
172 * YCbCr format default is BT601.
174 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
175 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
176 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
177 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
178 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
180 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
181 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
182 HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit
184 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
185 HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26,
186 HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/
187 HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/
188 HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/
190 HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 =
191 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12),
192 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 =
193 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO),
194 HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 =
195 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP),
196 HAL_PIXEL_FORMAT_YCrCb_444_BT709 =
197 BT709(HAL_PIXEL_FORMAT_YCrCb_444),
199 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 =
200 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
201 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 =
202 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
203 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 =
204 BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
206 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 =
207 BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
208 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 =
209 BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
210 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 =
211 BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
214 //display data format
235 #define IS_YUV_FMT(fmt) ((fmt >= YUV420) ? 1 : 0)
236 #define IS_RGB_FMT(fmt) ((fmt < YUV420) ? 1 : 0)
237 #define IS_FBDC_FMT(fmt) \
238 (((fmt >= FBDC_RGB_565) && (fmt <= FBDC_ABGR_888)) ? 1 : 0)
259 SCREEN_PREPARE_DDR_CHANGE = 0x0,
260 SCREEN_UNPREPARE_DDR_CHANGE,
264 GET_PAGE_FAULT = 0x0,
265 CLR_PAGE_FAULT = 0x1,
266 UNMASK_PAGE_FAULT = 0x2
269 enum rk_vop_feature {
270 SUPPORT_VOP_IDENTIFY = BIT(0),
271 SUPPORT_IFBDC = BIT(1),
272 SUPPORT_AFBDC = BIT(2),
273 SUPPORT_WRITE_BACK = BIT(3),
274 SUPPORT_YUV420_OUTPUT = BIT(4)
277 struct rk_vop_property {
283 enum rk_win_feature {
284 SUPPORT_WIN_IDENTIFY = BIT(0),
285 SUPPORT_SCALE = BIT(1),
286 SUPPORT_YUV = BIT(2),
287 SUPPORT_YUV10BIT = BIT(3),
288 SUPPORT_MULTI_AREA = BIT(4),
289 SUPPORT_HWC_LAYER = BIT(5)
292 struct rk_win_property {
299 struct fb_bitfield red;
300 struct fb_bitfield green;
301 struct fb_bitfield blue;
302 struct fb_bitfield transp;
305 struct rk_fb_frame_time {
306 u64 last_framedone_t;
312 wait_queue_head_t wait;
317 struct mutex irq_lock;
318 struct task_struct *thread;
321 struct color_key_cfg {
322 u32 win0_color_key_cfg;
323 u32 win1_color_key_cfg;
324 u32 win2_color_key_cfg;
333 const char *rgl_name;
338 struct rk_disp_pwr_ctr_list {
339 struct list_head list;
340 struct pwr_ctr pwr_ctr;
343 typedef enum _TRSP_MODE {
353 struct rk_lcdc_post_cfg {
360 struct rk_fb_wb_cfg {
370 struct rk_lcdc_bcsh {
379 struct rk_lcdc_win_area {
381 enum data_format format;
385 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
386 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
387 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
389 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
391 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
393 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
395 u16 xoff; /*mem offset*/
397 unsigned long smem_start;
398 unsigned long cbr_start; /*Cbr memory start address*/
399 #if defined(CONFIG_ION_ROCKCHIP)
400 struct ion_handle *ion_hdl;
402 struct dma_buf *dma_buf;
414 u8 fbdc_dsp_width_ratio;
416 u16 fbdc_mb_vir_width;
417 u16 fbdc_mb_vir_height;
423 u16 fbdc_cmp_index_init;
430 struct rk_win_property property;
431 bool state; /*on or off*/
432 bool last_state; /*on or off*/
434 int z_order; /*win sel layer*/
448 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
449 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
450 u8 yrgb_hsd_mode;//h scale down mode
451 u8 yrgb_vsu_mode;//v scale up mode
452 u8 yrgb_vsd_mode;//v scale down mode
471 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
472 struct rk_lcdc_post_cfg post_cfg;
475 struct rk_lcdc_driver;
477 struct rk_fb_trsm_ops {
479 int (*disable)(void);
480 int (*dsp_pwr_on) (void);
481 int (*dsp_pwr_off) (void);
484 struct rk_lcdc_drv_ops {
485 int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
486 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
487 int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
488 int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
489 unsigned long arg, int layer_id);
490 int (*suspend) (struct rk_lcdc_driver *dev_drv);
491 int (*resume) (struct rk_lcdc_driver *dev_drv);
492 int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
494 int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
495 int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
496 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
497 int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
498 ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
500 int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
501 int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv,
502 u16 *xact, u16 *yact, int *format,
503 u32 *dsp_addr, int *ymirror);
504 int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
505 int format, u16 xact, u16 yact, u16 xvir,
508 int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id);
509 int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
510 int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
511 int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
512 int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
513 u16 fb_win_map_order);
514 int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
515 int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut);
516 int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
517 int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
518 int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
519 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
520 int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
521 int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
522 int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
523 int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
524 int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
525 int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]);
526 int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global);
527 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
528 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
529 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
530 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
531 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
532 int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
533 int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
534 int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
535 int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
536 int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
537 struct overscan *overscan);
538 int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
539 int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable);
540 int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support);
541 int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd);
542 int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable);
543 int (*set_wb)(struct rk_lcdc_driver *dev_drv);
546 struct rk_fb_area_par {
547 u8 data_format; /*layer data fmt*/
553 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
555 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
557 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
559 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
569 struct rk_fb_win_par {
571 u8 z_order; /*win sel layer*/
575 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
579 struct rk_fb_win_cfg_data {
582 short rel_fence_fd[RK_MAX_BUF_NUM];
583 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
584 struct rk_fb_wb_cfg wb_cfg;
587 struct rk_fb_reg_wb_data {
590 struct ion_handle *ion_handle;
591 unsigned long smem_start;
592 unsigned long cbr_start; /*Cbr memory start address*/
597 struct rk_fb_reg_area_data {
598 struct sync_fence *acq_fence;
599 u8 data_format; /*layer data fmt*/
600 u8 index_buf; /*judge if the buffer is index*/
601 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
602 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
606 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
608 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
610 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
612 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
614 u16 xoff; /*mem offset*/
616 unsigned long smem_start;
617 unsigned long cbr_start; /*Cbr memory start address*/
619 struct ion_handle *ion_handle;
621 struct dma_buf *dma_buf;
622 struct dma_buf_attachment *attachment;
623 struct sg_table *sg_table;
631 struct rk_fb_reg_win_data {
633 int z_order; /*win sel layer*/
634 u32 area_num; /*maybe two region have the same dma buff,*/
635 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
642 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
645 struct rk_fb_reg_data {
646 struct list_head list;
650 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
651 struct rk_fb_reg_wb_data reg_wb_data;
654 struct rk_lcdc_driver {
660 struct rk_vop_property property;
662 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
663 struct rk_fb_reg_wb_data wb_data;
665 int num_buf; //the num_of buffer
667 int fb_index_base; //the first fb index of the lcdc device
668 struct rk_screen *screen0; //some platform have only one lcdc,but extend
669 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
670 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
684 char mmu_dts_name[40];
685 struct device *mmu_dev;
688 struct rk_fb_reg_area_data reg_area_data;
690 * front_regs means this config is scaning on the devices.
692 struct rk_fb_reg_data *front_regs;
693 struct mutex front_lock;
695 struct mutex fb_win_id_mutex;
696 struct mutex win_config;
698 struct mutex switch_screen; /*for switch screen*/
699 struct completion frame_done; /*sync for pan_display,whe we set a new
700 frame address to lcdc register,we must
701 make sure the frame begain to display*/
702 spinlock_t cpl_lock; /*lock for completion frame done */
704 struct rk_fb_vsync vsync_info;
705 struct rk_fb_frame_time frame_time;
706 int wait_fs; /*wait for new frame start in kernel */
707 struct sw_sync_timeline *timeline;
711 struct list_head update_regs_list;
712 struct list_head saved_list;
713 struct mutex update_regs_list_lock;
714 struct kthread_worker update_regs_worker;
715 struct task_struct *update_regs_thread;
716 struct kthread_work update_regs_work;
717 wait_queue_head_t update_regs_wait;
719 struct mutex output_lock;
720 struct rk29fb_info *screen_ctr_info;
721 struct list_head pwrlist_head;
722 struct rk_lcdc_drv_ops *ops;
723 struct rk_fb_trsm_ops *trsm_ops;
724 #ifdef CONFIG_DRM_ROCKCHIP
725 void (*irq_call_back)(struct rk_lcdc_driver *driver);
727 struct overscan overscan;
728 struct rk_lcdc_bcsh bcsh;
731 int bcsh_init_status;
734 /*1:hdmi switch uncomplete,0:complete*/
737 struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM];
738 struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM];
739 unsigned int area_support[RK30_MAX_LAYER_SUPPORT];
746 unsigned long fb_phy_base; /* Start of fb address (physical address) */
747 char __iomem *fb_virt_base; /* Start of fb address (virt address) */
749 struct rk_lcdc_driver *lcdc_drv;
751 #if defined(CONFIG_ION_ROCKCHIP)
752 struct ion_handle *ion_hdl;
757 /*disp_mode: dual display mode
758 * NO_DUAL,no dual display,
759 ONE_DUAL,use one lcdc + rk61x for dual display
760 DUAL,use 2 lcdcs for dual display
761 num_fb: the total number of fb
762 num_lcdc: the total number of lcdc
768 struct rk29fb_info *mach_info;
769 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
771 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
774 #if defined(CONFIG_ION_ROCKCHIP)
775 struct ion_client *ion_client;
779 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
780 extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
781 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
782 struct rk_lcdc_win *win, int id);
783 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
784 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
785 extern int rk_fb_get_extern_screen(struct rk_screen *screen);
786 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
787 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
788 extern u32 rk_fb_get_prmry_screen_pixclock(void);
789 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
790 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
791 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
792 extern bool is_prmry_rk_lcdc_registered(void);
793 extern int rk_fb_prase_timing_dt(struct device_node *np,
794 struct rk_screen *screen);
795 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
797 extern int rk_fb_dpi_open(bool open);
798 extern int rk_fb_dpi_layer_sel(int layer_id);
799 extern int rk_fb_dpi_status(void);
801 extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
802 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
803 extern int rkfb_create_sysfs(struct fb_info *fbi);
804 extern char *get_format_string(enum data_format, char *fmt);
805 extern int support_uboot_display(void);
806 extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
807 extern int rk_get_real_fps(int time);
808 extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
809 extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
811 int rk_fb_get_display_policy(void);
812 int rk_fb_pixel_width(int data_format);
813 void trace_buffer_dump(struct device *dev,
814 struct rk_lcdc_driver *dev_drv);
815 extern int rockchip_get_screen_type(void);