1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include<linux/completion.h>
21 #include<linux/spinlock.h>
22 #include<asm/atomic.h>
23 #include <mach/board.h>
26 #define RK30_MAX_LCDC_SUPPORT 4
27 #define RK30_MAX_LAYER_SUPPORT 4
28 #define RK_MAX_FB_SUPPORT 4
32 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
33 #define FB0_IOCTL_SET_PANEL 0x6002
39 #define FB0_IOCTL_SET_BUF 0x6017
40 #define FB0_IOCTL_COPY_CURBUF 0x6018
41 #define FB0_IOCTL_CLOSE_BUF 0x6019
44 #define FB1_IOCTL_GET_PANEL_SIZE 0x5001
45 #define FB1_IOCTL_SET_YUV_ADDR 0x5002
46 //#define FB1_TOCTL_SET_MCU_DIR 0x5003
47 #define FB1_IOCTL_SET_ROTATE 0x5003
48 #define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
49 #define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
50 #define FB1_IOCTL_SET_WIN0_TOP 0x5018
52 /********************************************************************
53 ** display output interface supported by rk lcdc *
54 ********************************************************************/
62 #define OUT_S888DUMY 12
63 #define OUT_P16BPP4 24 //
64 #define OUT_D888_P666 0x21 //
65 #define OUT_D888_P565 0x22 //
69 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
73 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
74 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
75 HAL_PIXEL_FORMAT_RGB_888 = 3,
76 HAL_PIXEL_FORMAT_RGB_565 = 4,
77 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
78 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
79 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
81 /* 0x8 - 0xFF range unavailable */
86 * This range is reserved for pixel formats that are specific to the HAL
87 * implementation. Implementations can use any value in this range to
88 * communicate video pixel formats between their HAL modules. These formats
89 * must not have an alpha channel. Additionally, an EGLimage created from a
90 * gralloc buffer of one of these formats must be supported for use with the
91 * GL_OES_EGL_image_external OpenGL ES extension.
97 * This format is exposed outside of the HAL to software decoders and
98 * applications. EGLImageKHR must support it in conjunction with the
99 * OES_EGL_image_external extension.
101 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
102 * by (W/2) x (H/2) Cr and Cb planes.
104 * This format assumes
107 * - a horizontal stride multiple of 16 pixels
108 * - a vertical stride equal to the height
110 * y_size = stride * height
111 * c_size = ALIGN(stride/2, 16) * height/2
112 * size = y_size + c_size * 2
114 * cb_offset = y_size + c_size
117 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
121 /* Legacy formats (deprecated), used by ImageFormat.java */
122 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
123 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
124 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
125 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
126 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
127 HAL_PIXEL_FORMAT_YCrCb_444 = 0x22, //yuv444
133 //display data format
144 struct fb_bitfield red;
145 struct fb_bitfield green;
146 struct fb_bitfield blue;
147 struct fb_bitfield transp;
150 typedef enum _TRSP_MODE
164 bool state; //on or off
166 u32 y_offset; //yuv/rgb offset -->LCDC_WINx_YRGB_MSTx
167 u32 c_offset; //cb cr offset--->LCDC_WINx_CBR_MSTx
168 u32 xpos; //start point in panel --->LCDC_WINx_DSP_ST
170 u16 xsize; // display window width/height -->LCDC_WINx_DSP_INFO
172 u16 xact; //origin display window size -->LCDC_WINx_ACT_INFO
174 u16 xvir; //virtual width/height -->LCDC_WINx_VIR
176 unsigned long smem_start;
177 unsigned long cbr_start; // Cbr memory start address
178 enum data_format format;
184 struct rk_lcdc_device_driver{
189 struct layer_par *layer_par[RK_MAX_FB_SUPPORT];
190 struct layer_par *def_layer_par;
192 int fb_index_base; //the first fb index of the lcdc device
196 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
197 spinlock_t cpl_lock; //lock for completion frame done
200 struct rk29fb_info *screen_ctr_info;
201 int (*open)(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open);
202 int (*init_lcdc)(struct rk_lcdc_device_driver *dev_drv);
203 int (*ioctl)(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id);
204 int (*suspend)(struct rk_lcdc_device_driver *dev_drv);
205 int (*resume)(struct rk_lcdc_device_driver *dev_drv);
206 int (*blank)(struct rk_lcdc_device_driver *dev_drv,int layer_id,int blank_mode);
207 int (*set_par)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
208 int (*pan_display)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
209 int (*get_disp_info)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
210 int (*load_screen)(struct rk_lcdc_device_driver *dev_drv, bool initscreen);
211 int (*get_layer_state)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
216 struct rk29fb_info * mach_info; //lcd io control info
217 struct fb_info *fb[RK_MAX_FB_SUPPORT];
220 struct rk_lcdc_device_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
223 int video_mode; //when play video set it to 1
224 struct workqueue_struct *workqueue;
225 struct delayed_work delay_work;
227 extern int rk_fb_register(struct rk_lcdc_device_driver *dev_drv,
228 struct rk_lcdc_device_driver *def_drv,int id);
229 extern int rk_fb_unregister(struct rk_lcdc_device_driver *dev_drv);
230 extern int get_fb_layer_id(struct fb_fix_screeninfo *fix);
231 extern struct rk_lcdc_device_driver * rk_get_lcdc_drv(char *name);
232 extern int rk_fb_switch_screen(rk_screen *screen ,int enable ,int lcdc_id);
233 extern int rkfb_create_sysfs(struct fb_info *fbi);