1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 2
34 #define RK30_MAX_LAYER_SUPPORT 5
35 #define RK_MAX_FB_SUPPORT 5
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 11
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
57 #define RK_FBIOSET_HWC_ADDR 0x4624
59 #define RK_FBIOGET_DMABUF_FD 0x5003
60 #define RK_FBIOSET_DMABUF_FD 0x5004
61 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
62 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
63 #define RK_FBIOSET_OVERLAY_STA 0x5018
64 #define RK_FBIOGET_OVERLAY_STA 0X4619
65 #define RK_FBIOSET_ENABLE 0x5019
66 #define RK_FBIOGET_ENABLE 0x5020
67 #define RK_FBIOSET_CONFIG_DONE 0x4628
68 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
69 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
70 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
71 #define RK_FBIOGET_DSP_ADDR 0x4630
72 #define RK_FBIOGET_LIST_STA 0X4631
73 #define RK_FBIOGET_IOMMU_STA 0x4632
74 #define RK_FBIOSET_CLEAR_FB 0x4633
78 #define RK_LF_STATUS_FC 0xef
79 #define RK_LF_STATUS_FR 0xee
80 #define RK_LF_STATUS_NC 0xfe
81 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
84 /* x y mirror or rotate mode */
86 #define X_MIRROR 1 /* up-down flip*/
87 #define Y_MIRROR 2 /* left-right flip */
88 #define X_Y_MIRROR 3 /* the same as rotate 180 degrees */
89 #define ROTATE_90 4 /* clockwise rotate 90 degrees */
90 #define ROTATE_180 8 /* rotate 180 degrees
91 * It is recommended to use X_Y_MIRROR
92 * rather than ROTATE_180
94 #define ROTATE_270 12 /* clockwise rotate 270 degrees */
98 * pixel align value for gpu,align as 64 bytes in an odd number of times
100 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
101 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
102 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
103 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
104 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
106 #define DUMP_FRAME_NUM 3
108 //#define USE_ION_MMU 1
109 #if defined(CONFIG_ION_ROCKCHIP)
110 extern struct ion_client *rockchip_ion_client_create(const char *name);
113 extern int rk_fb_poll_prmry_screen_vblank(void);
114 extern u32 rk_fb_get_prmry_screen_ft(void);
115 extern u32 rk_fb_get_prmry_screen_vbt(void);
116 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
117 extern int rk_fb_set_prmry_screen_status(int status);
118 extern bool rk_fb_poll_wait_frame_complete(void);
120 /********************************************************************
121 ** display output interface supported by rockchip lcdc *
122 ********************************************************************/
124 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
125 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
128 #define OUT_CCIR656 6
130 #define OUT_S888DUMY 12
131 #define OUT_YUV_420 14
132 #define OUT_P101010 15
133 #define OUT_YUV_420_10BIT 16
134 #define OUT_P16BPP4 24
135 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
136 #define OUT_D888_P565 0x22
144 #define CSC_MASK (0x3 << CSC_SHIFT)
145 #define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT)
147 #define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK))
148 #define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK))
149 #define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK))
152 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
155 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
156 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
157 HAL_PIXEL_FORMAT_RGB_888 = 3,
158 HAL_PIXEL_FORMAT_RGB_565 = 4,
159 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
160 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
161 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
163 /* 0x8 - 0xFF range unavailable */
168 * This range is reserved for pixel formats that are specific to the HAL
169 * implementation. Implementations can use any value in this range to
170 * communicate video pixel formats between their HAL modules. These formats
171 * must not have an alpha channel. Additionally, an EGLimage created from a
172 * gralloc buffer of one of these formats must be supported for use with the
173 * GL_OES_EGL_image_external OpenGL ES extension.
177 * Android YUV format:
179 * This format is exposed outside of the HAL to software decoders and
180 * applications. EGLImageKHR must support it in conjunction with the
181 * OES_EGL_image_external extension.
183 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
184 * by (W/2) x (H/2) Cr and Cb planes.
186 * This format assumes
189 * - a horizontal stride multiple of 16 pixels
190 * - a vertical stride equal to the height
192 * y_size = stride * height
193 * c_size = ALIGN(stride/2, 16) * height/2
194 * size = y_size + c_size * 2
196 * cb_offset = y_size + c_size
199 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
201 /* Legacy formats (deprecated), used by ImageFormat.java */
204 * YCbCr format default is BT601.
206 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
207 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
208 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
209 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
210 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
212 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
213 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
214 HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit
216 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
217 HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26,
218 HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/
219 HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/
220 HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/
222 HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 =
223 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12),
224 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 =
225 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO),
226 HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 =
227 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP),
228 HAL_PIXEL_FORMAT_YCrCb_444_BT709 =
229 BT709(HAL_PIXEL_FORMAT_YCrCb_444),
231 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 =
232 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
233 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 =
234 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
235 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 =
236 BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
238 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 =
239 BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
240 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 =
241 BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
242 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 =
243 BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
246 //display data format
286 SCREEN_PREPARE_DDR_CHANGE = 0x0,
287 SCREEN_UNPREPARE_DDR_CHANGE,
291 GET_PAGE_FAULT = 0x0,
292 CLR_PAGE_FAULT = 0x1,
293 UNMASK_PAGE_FAULT = 0x2
297 struct fb_bitfield red;
298 struct fb_bitfield green;
299 struct fb_bitfield blue;
300 struct fb_bitfield transp;
303 struct rk_fb_frame_time {
304 u64 last_framedone_t;
310 wait_queue_head_t wait;
315 struct mutex irq_lock;
316 struct task_struct *thread;
319 struct color_key_cfg {
320 u32 win0_color_key_cfg;
321 u32 win1_color_key_cfg;
322 u32 win2_color_key_cfg;
331 const char *rgl_name;
336 struct rk_disp_pwr_ctr_list {
337 struct list_head list;
338 struct pwr_ctr pwr_ctr;
341 typedef enum _TRSP_MODE {
351 struct rk_lcdc_post_cfg {
358 struct rk_lcdc_bcsh {
367 struct rk_lcdc_win_area {
369 enum data_format format;
373 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
374 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
375 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
377 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
379 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
381 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
383 u16 xoff; /*mem offset*/
385 unsigned long smem_start;
386 unsigned long cbr_start; /*Cbr memory start address*/
387 #if defined(CONFIG_ION_ROCKCHIP)
388 struct ion_handle *ion_hdl;
390 struct dma_buf *dma_buf;
402 u8 fbdc_dsp_width_ratio;
404 u16 fbdc_mb_vir_width;
405 u16 fbdc_mb_vir_height;
411 u16 fbdc_cmp_index_init;
418 bool state; /*on or off*/
419 bool last_state; /*on or off*/
421 int z_order; /*win sel layer*/
435 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
436 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
437 u8 yrgb_hsd_mode;//h scale down mode
438 u8 yrgb_vsu_mode;//v scale up mode
439 u8 yrgb_vsd_mode;//v scale down mode
457 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
458 struct rk_lcdc_post_cfg post_cfg;
461 struct rk_lcdc_driver;
463 struct rk_fb_trsm_ops {
465 int (*disable)(void);
466 int (*dsp_pwr_on) (void);
467 int (*dsp_pwr_off) (void);
470 struct rk_lcdc_drv_ops {
471 int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
472 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
473 int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
474 int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
475 unsigned long arg, int layer_id);
476 int (*suspend) (struct rk_lcdc_driver *dev_drv);
477 int (*resume) (struct rk_lcdc_driver *dev_drv);
478 int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
480 int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
481 int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
482 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
483 int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
484 ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
486 int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
487 int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv,
488 u16 *xact, u16 *yact, int *format,
490 int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
491 int format, u16 xact, u16 yact, u16 xvir);
493 int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id);
494 int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
495 int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
496 int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
497 int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
498 u16 fb_win_map_order);
499 int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
500 int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut);
501 int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
502 int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
503 int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
504 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
505 int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
506 int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
507 int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
508 int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
509 int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
510 int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]);
511 int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global);
512 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
513 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
514 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
515 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
516 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
517 int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
518 int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
519 int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
520 int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
521 int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
522 struct overscan *overscan);
523 int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
524 int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable);
525 int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support);
526 int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd);
527 int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable);
530 struct rk_fb_area_par {
531 u8 data_format; /*layer data fmt*/
537 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
539 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
541 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
543 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
553 struct rk_fb_win_par {
555 u8 z_order; /*win sel layer*/
559 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
563 struct rk_fb_win_cfg_data {
566 short rel_fence_fd[RK_MAX_BUF_NUM];
567 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
568 struct rk_lcdc_post_cfg post_cfg;
571 struct rk_fb_reg_area_data {
572 struct sync_fence *acq_fence;
573 u8 data_format; /*layer data fmt*/
574 u8 index_buf; /*judge if the buffer is index*/
575 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
576 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
580 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
582 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
584 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
586 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
588 u16 xoff; /*mem offset*/
590 unsigned long smem_start;
591 unsigned long cbr_start; /*Cbr memory start address*/
593 struct ion_handle *ion_handle;
595 struct dma_buf *dma_buf;
596 struct dma_buf_attachment *attachment;
597 struct sg_table *sg_table;
605 struct rk_fb_reg_win_data {
607 int z_order; /*win sel layer*/
608 u32 area_num; /*maybe two region have the same dma buff,*/
609 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
616 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
619 struct rk_fb_reg_data {
620 struct list_head list;
624 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
625 struct rk_lcdc_post_cfg post_cfg;
628 struct rk_lcdc_driver {
635 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
637 int num_buf; //the num_of buffer
639 int fb_index_base; //the first fb index of the lcdc device
640 struct rk_screen *screen0; //some platform have only one lcdc,but extend
641 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
642 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
656 char mmu_dts_name[40];
657 struct device *mmu_dev;
660 struct rk_fb_reg_area_data reg_area_data;
662 * front_regs means this config is scaning on the devices.
664 struct rk_fb_reg_data *front_regs;
665 struct mutex front_lock;
667 struct mutex fb_win_id_mutex;
668 struct mutex win_config;
670 struct mutex switch_screen; /*for switch screen*/
671 struct completion frame_done; /*sync for pan_display,whe we set a new
672 frame address to lcdc register,we must
673 make sure the frame begain to display*/
674 spinlock_t cpl_lock; /*lock for completion frame done */
676 struct rk_fb_vsync vsync_info;
677 struct rk_fb_frame_time frame_time;
678 int wait_fs; /*wait for new frame start in kernel */
679 struct sw_sync_timeline *timeline;
683 struct list_head update_regs_list;
684 struct list_head saved_list;
685 struct mutex update_regs_list_lock;
686 struct kthread_worker update_regs_worker;
687 struct task_struct *update_regs_thread;
688 struct kthread_work update_regs_work;
689 wait_queue_head_t update_regs_wait;
691 struct mutex output_lock;
692 struct rk29fb_info *screen_ctr_info;
693 struct list_head pwrlist_head;
694 struct rk_lcdc_drv_ops *ops;
695 struct rk_fb_trsm_ops *trsm_ops;
696 #ifdef CONFIG_DRM_ROCKCHIP
697 void (*irq_call_back)(struct rk_lcdc_driver *driver);
699 struct overscan overscan;
700 struct rk_lcdc_bcsh bcsh;
703 int bcsh_init_status;
706 /*1:hdmi switch uncomplete,0:complete*/
709 struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM];
710 struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM];
711 unsigned int area_support[RK30_MAX_LAYER_SUPPORT];
718 unsigned long fb_phy_base; /* Start of fb address (physical address) */
719 char __iomem *fb_virt_base; /* Start of fb address (virt address) */
721 struct rk_lcdc_driver *lcdc_drv;
723 #if defined(CONFIG_ION_ROCKCHIP)
724 struct ion_handle *ion_hdl;
729 /*disp_mode: dual display mode
730 * NO_DUAL,no dual display,
731 ONE_DUAL,use one lcdc + rk61x for dual display
732 DUAL,use 2 lcdcs for dual display
733 num_fb: the total number of fb
734 num_lcdc: the total number of lcdc
740 struct rk29fb_info *mach_info;
741 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
743 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
746 #if defined(CONFIG_ION_ROCKCHIP)
747 struct ion_client *ion_client;
751 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
752 extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
753 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
754 struct rk_lcdc_win *win, int id);
755 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
756 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
757 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
758 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
759 extern u32 rk_fb_get_prmry_screen_pixclock(void);
760 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
761 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
762 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
763 extern bool is_prmry_rk_lcdc_registered(void);
764 extern int rk_fb_prase_timing_dt(struct device_node *np,
765 struct rk_screen *screen);
766 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
768 extern int rk_fb_dpi_open(bool open);
769 extern int rk_fb_dpi_layer_sel(int layer_id);
770 extern int rk_fb_dpi_status(void);
772 extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
773 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
774 extern int rkfb_create_sysfs(struct fb_info *fbi);
775 extern char *get_format_string(enum data_format, char *fmt);
776 extern int support_uboot_display(void);
777 extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
778 extern int rk_get_real_fps(int time);
779 extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
780 extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
782 int rk_fb_get_display_policy(void);
783 int rk_fb_pixel_width(int data_format);
784 void trace_buffer_dump(struct device *dev,
785 struct rk_lcdc_driver *dev_drv);
786 extern int rockchip_get_screen_type(void);