1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/display/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/version.h>
35 #define RK30_MAX_LCDC_SUPPORT 2
36 #define RK30_MAX_LAYER_SUPPORT 5
37 #define RK_MAX_FB_SUPPORT 5
38 #define RK_WIN_MAX_AREA 4
39 #define RK_MAX_BUF_NUM 11
41 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
42 #define FB0_IOCTL_SET_PANEL 0x6002
48 #define FB0_IOCTL_SET_BUF 0x6017
49 #define FB0_IOCTL_COPY_CURBUF 0x6018
50 #define FB0_IOCTL_CLOSE_BUF 0x6019
53 #define RK_FBIOGET_PANEL_SIZE 0x5001
54 #define RK_FBIOSET_YUV_ADDR 0x5002
55 #define RK_FBIOGET_SCREEN_STATE 0X4620
56 #define RK_FBIOGET_16OR32 0X4621
57 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
58 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
59 #define RK_FBIOSET_HWC_ADDR 0x4624
61 #define RK_FBIOGET_DMABUF_FD 0x5003
62 #define RK_FBIOSET_DMABUF_FD 0x5004
63 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
64 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
65 #define RK_FBIOSET_OVERLAY_STA 0x5018
66 #define RK_FBIOGET_OVERLAY_STA 0X4619
67 #define RK_FBIOSET_ENABLE 0x5019
68 #define RK_FBIOGET_ENABLE 0x5020
69 #define RK_FBIOSET_CONFIG_DONE 0x4628
70 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
71 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
72 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
73 #define RK_FBIOGET_DSP_ADDR 0x4630
74 #define RK_FBIOGET_LIST_STA 0X4631
75 #define RK_FBIOGET_IOMMU_STA 0x4632
76 #define RK_FBIOSET_CLEAR_FB 0x4633
80 #define RK_LF_STATUS_FC 0xef
81 #define RK_LF_STATUS_FR 0xee
82 #define RK_LF_STATUS_NC 0xfe
83 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
86 * pixel align value for gpu,align as 64 bytes in an odd number of times
88 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
89 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
90 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
91 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
92 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
94 #define DUMP_FRAME_NUM 3
96 //#define USE_ION_MMU 1
97 #if defined(CONFIG_ION_ROCKCHIP)
98 extern struct ion_client *rockchip_ion_client_create(const char *name);
101 extern int rk_fb_poll_prmry_screen_vblank(void);
102 extern u32 rk_fb_get_prmry_screen_ft(void);
103 extern u32 rk_fb_get_prmry_screen_vbt(void);
104 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
105 extern int rk_fb_set_prmry_screen_status(int status);
106 extern bool rk_fb_poll_wait_frame_complete(void);
114 #define CSC_MASK (0x3 << CSC_SHIFT)
115 #define CSC_FORMAT(x) (((x) & CSC_MASK) >> CSC_SHIFT)
117 #define BT601(x) ((CSC_BT601 << CSC_SHIFT) | ((x) & ~CSC_MASK))
118 #define BT709(x) ((CSC_BT709 << CSC_SHIFT) | ((x) & ~CSC_MASK))
119 #define BT2020(x) ((CSC_BT2020 << CSC_SHIFT) | ((x) & ~CSC_MASK))
122 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
125 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
126 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
127 HAL_PIXEL_FORMAT_RGB_888 = 3,
128 HAL_PIXEL_FORMAT_RGB_565 = 4,
129 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
130 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
131 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
133 /* 0x8 - 0xFF range unavailable */
138 * This range is reserved for pixel formats that are specific to the HAL
139 * implementation. Implementations can use any value in this range to
140 * communicate video pixel formats between their HAL modules. These formats
141 * must not have an alpha channel. Additionally, an EGLimage created from a
142 * gralloc buffer of one of these formats must be supported for use with the
143 * GL_OES_EGL_image_external OpenGL ES extension.
147 * Android YUV format:
149 * This format is exposed outside of the HAL to software decoders and
150 * applications. EGLImageKHR must support it in conjunction with the
151 * OES_EGL_image_external extension.
153 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
154 * by (W/2) x (H/2) Cr and Cb planes.
156 * This format assumes
159 * - a horizontal stride multiple of 16 pixels
160 * - a vertical stride equal to the height
162 * y_size = stride * height
163 * c_size = ALIGN(stride/2, 16) * height/2
164 * size = y_size + c_size * 2
166 * cb_offset = y_size + c_size
169 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
171 /* Legacy formats (deprecated), used by ImageFormat.java */
174 * YCbCr format default is BT601.
176 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
177 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
178 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
179 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
180 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
182 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
183 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
184 HAL_PIXEL_FORMAT_YCrCb_444_SP_10 = 0x24, //YUV444_1obit
186 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
187 HAL_PIXEL_FORMAT_FBDC_RGB565 = 0x26,
188 HAL_PIXEL_FORMAT_FBDC_U8U8U8U8 = 0x27, /*ARGB888*/
189 HAL_PIXEL_FORMAT_FBDC_U8U8U8 = 0x28, /*RGBP888*/
190 HAL_PIXEL_FORMAT_FBDC_RGBA888 = 0x29, /*ABGR888*/
191 HAL_PIXEL_FORMAT_BGRX_8888 = 0x30,
192 HAL_PIXEL_FORMAT_BGR_888 = 0x31,
193 HAL_PIXEL_FORMAT_BGR_565 = 0x32,
195 HAL_PIXEL_FORMAT_YCrCb_NV12_BT709 =
196 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12),
197 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO_BT709 =
198 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO),
199 HAL_PIXEL_FORMAT_YCbCr_422_SP_BT709 =
200 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP),
201 HAL_PIXEL_FORMAT_YCrCb_444_BT709 =
202 BT709(HAL_PIXEL_FORMAT_YCrCb_444),
204 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT709 =
205 BT709(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
206 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT709 =
207 BT709(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
208 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT709 =
209 BT709(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
211 HAL_PIXEL_FORMAT_YCrCb_NV12_10_BT2020 =
212 BT2020(HAL_PIXEL_FORMAT_YCrCb_NV12_10),
213 HAL_PIXEL_FORMAT_YCbCr_422_SP_10_BT2020 =
214 BT2020(HAL_PIXEL_FORMAT_YCbCr_422_SP_10),
215 HAL_PIXEL_FORMAT_YCrCb_420_SP_10_BT2020 =
216 BT2020(HAL_PIXEL_FORMAT_YCrCb_444_SP_10),
219 //display data format
241 #define IS_YUV_FMT(fmt) ((fmt >= YUV420) ? 1 : 0)
242 #define IS_RGB_FMT(fmt) ((fmt < YUV420) ? 1 : 0)
243 #define IS_FBDC_FMT(fmt) \
244 (((fmt >= FBDC_RGB_565) && (fmt <= FBDC_ABGR_888)) ? 1 : 0)
265 SCREEN_PREPARE_DDR_CHANGE = 0x0,
266 SCREEN_UNPREPARE_DDR_CHANGE,
270 GET_PAGE_FAULT = 0x0,
271 CLR_PAGE_FAULT = 0x1,
272 UNMASK_PAGE_FAULT = 0x2
275 enum rk_vop_feature {
276 SUPPORT_VOP_IDENTIFY = BIT(0),
277 SUPPORT_IFBDC = BIT(1),
278 SUPPORT_AFBDC = BIT(2),
279 SUPPORT_WRITE_BACK = BIT(3),
280 SUPPORT_YUV420_OUTPUT = BIT(4)
283 struct rk_vop_property {
289 enum rk_win_feature {
290 SUPPORT_WIN_IDENTIFY = BIT(0),
291 SUPPORT_SCALE = BIT(1),
292 SUPPORT_YUV = BIT(2),
293 SUPPORT_YUV10BIT = BIT(3),
294 SUPPORT_MULTI_AREA = BIT(4),
295 SUPPORT_HWC_LAYER = BIT(5)
298 struct rk_win_property {
305 struct fb_bitfield red;
306 struct fb_bitfield green;
307 struct fb_bitfield blue;
308 struct fb_bitfield transp;
311 struct rk_fb_frame_time {
312 u64 last_framedone_t;
318 wait_queue_head_t wait;
323 struct mutex irq_lock;
324 struct task_struct *thread;
327 struct color_key_cfg {
328 u32 win0_color_key_cfg;
329 u32 win1_color_key_cfg;
330 u32 win2_color_key_cfg;
339 const char *rgl_name;
344 struct rk_disp_pwr_ctr_list {
345 struct list_head list;
346 struct pwr_ctr pwr_ctr;
349 typedef enum _TRSP_MODE {
359 struct rk_lcdc_post_cfg {
366 struct rk_fb_wb_cfg {
376 struct rk_lcdc_bcsh {
385 struct rk_lcdc_win_area {
387 enum data_format format;
391 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
392 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
393 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
395 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
397 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
399 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
401 u16 xoff; /*mem offset*/
403 unsigned long smem_start;
404 unsigned long cbr_start; /*Cbr memory start address*/
405 #if defined(CONFIG_ION_ROCKCHIP)
406 struct ion_handle *ion_hdl;
408 struct dma_buf *dma_buf;
420 u8 fbdc_dsp_width_ratio;
422 u16 fbdc_mb_vir_width;
423 u16 fbdc_mb_vir_height;
429 u16 fbdc_cmp_index_init;
436 struct rk_win_property property;
437 bool state; /*on or off*/
438 bool last_state; /*on or off*/
440 int z_order; /*win sel layer*/
454 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
455 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
456 u8 yrgb_hsd_mode;//h scale down mode
457 u8 yrgb_vsu_mode;//v scale up mode
458 u8 yrgb_vsd_mode;//v scale down mode
477 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
478 struct rk_lcdc_post_cfg post_cfg;
481 struct rk_lcdc_driver;
483 struct rk_fb_trsm_ops {
485 int (*disable)(void);
486 int (*dsp_pwr_on) (void);
487 int (*dsp_pwr_off) (void);
490 struct rk_lcdc_drv_ops {
491 int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
492 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
493 int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
494 int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
495 unsigned long arg, int layer_id);
496 int (*suspend) (struct rk_lcdc_driver *dev_drv);
497 int (*resume) (struct rk_lcdc_driver *dev_drv);
498 int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
500 int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
501 int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
502 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
503 int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
504 ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
506 int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
507 int (*get_dspbuf_info) (struct rk_lcdc_driver *dev_drv,
508 u16 *xact, u16 *yact, int *format,
509 u32 *dsp_addr, int *ymirror);
510 int (*post_dspbuf)(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
511 int format, u16 xact, u16 yact, u16 xvir,
514 int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id, int area_id);
515 int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
516 int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
517 int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
518 int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
519 u16 fb_win_map_order);
520 int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
521 int (*set_cabc_lut)(struct rk_lcdc_driver *dev_drv, int *lut);
522 int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
523 int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
524 int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
525 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
526 int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
527 int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
528 int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
529 int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
530 int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
531 int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv, unsigned int dsp_addr[][4]);
532 int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode, int calc, int up, int down, int global);
533 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
534 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
535 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
536 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
537 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
538 int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
539 int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
540 int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
541 int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
542 int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
543 struct overscan *overscan);
544 int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
545 int (*backlight_close)(struct rk_lcdc_driver *dev_drv, int enable);
546 int (*area_support_num)(struct rk_lcdc_driver *dev_drv, unsigned int *area_support);
547 int (*extern_func)(struct rk_lcdc_driver *dev_drv, int cmd);
548 int (*wait_frame_start)(struct rk_lcdc_driver *dev_drv, int enable);
549 int (*set_wb)(struct rk_lcdc_driver *dev_drv);
552 struct rk_fb_area_par {
553 u8 data_format; /*layer data fmt*/
559 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
561 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
563 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
565 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
575 struct rk_fb_win_par {
577 u8 z_order; /*win sel layer*/
581 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
585 struct rk_fb_win_cfg_data {
588 short rel_fence_fd[RK_MAX_BUF_NUM];
589 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
590 struct rk_fb_wb_cfg wb_cfg;
593 struct rk_fb_reg_wb_data {
596 struct ion_handle *ion_handle;
597 unsigned long smem_start;
598 unsigned long cbr_start; /*Cbr memory start address*/
603 struct rk_fb_reg_area_data {
604 struct sync_fence *acq_fence;
605 u8 data_format; /*layer data fmt*/
606 u8 index_buf; /*judge if the buffer is index*/
607 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
608 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
612 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
614 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
616 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
618 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
620 u16 xoff; /*mem offset*/
622 unsigned long smem_start;
623 unsigned long cbr_start; /*Cbr memory start address*/
625 struct ion_handle *ion_handle;
627 struct dma_buf *dma_buf;
628 struct dma_buf_attachment *attachment;
629 struct sg_table *sg_table;
637 struct rk_fb_reg_win_data {
639 int z_order; /*win sel layer*/
640 u32 area_num; /*maybe two region have the same dma buff,*/
641 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
648 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
651 struct rk_fb_reg_data {
652 struct list_head list;
656 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
657 struct rk_fb_reg_wb_data reg_wb_data;
660 struct rk_lcdc_driver {
666 struct rk_vop_property property;
668 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
669 struct rk_fb_reg_wb_data wb_data;
671 int num_buf; //the num_of buffer
673 int fb_index_base; //the first fb index of the lcdc device
674 struct rk_screen *screen0; //some platform have only one lcdc,but extend
675 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
676 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
690 char mmu_dts_name[40];
691 struct device *mmu_dev;
694 struct rk_fb_reg_area_data reg_area_data;
696 * front_regs means this config is scaning on the devices.
698 struct rk_fb_reg_data *front_regs;
699 struct mutex front_lock;
701 struct mutex fb_win_id_mutex;
702 struct mutex win_config;
704 struct mutex switch_screen; /*for switch screen*/
705 struct completion frame_done; /*sync for pan_display,whe we set a new
706 frame address to lcdc register,we must
707 make sure the frame begain to display*/
708 spinlock_t cpl_lock; /*lock for completion frame done */
710 struct rk_fb_vsync vsync_info;
711 struct rk_fb_frame_time frame_time;
712 int wait_fs; /*wait for new frame start in kernel */
713 struct sw_sync_timeline *timeline;
717 struct list_head update_regs_list;
718 struct list_head saved_list;
719 struct mutex update_regs_list_lock;
720 struct kthread_worker update_regs_worker;
721 struct task_struct *update_regs_thread;
722 struct kthread_work update_regs_work;
723 wait_queue_head_t update_regs_wait;
725 struct mutex output_lock;
726 struct rk29fb_info *screen_ctr_info;
727 struct list_head pwrlist_head;
728 struct rk_lcdc_drv_ops *ops;
729 struct rk_fb_trsm_ops *trsm_ops;
730 #ifdef CONFIG_DRM_ROCKCHIP
731 void (*irq_call_back)(struct rk_lcdc_driver *driver);
733 struct overscan overscan;
734 struct rk_lcdc_bcsh bcsh;
737 int bcsh_init_status;
740 /*1:hdmi switch uncomplete,0:complete*/
743 struct rk_fb_win_cfg_data tmp_win_cfg[DUMP_FRAME_NUM];
744 struct rk_fb_reg_data tmp_regs[DUMP_FRAME_NUM];
745 unsigned int area_support[RK30_MAX_LAYER_SUPPORT];
752 unsigned long fb_phy_base; /* Start of fb address (physical address) */
753 char __iomem *fb_virt_base; /* Start of fb address (virt address) */
755 struct rk_lcdc_driver *lcdc_drv;
757 #if defined(CONFIG_ION_ROCKCHIP)
758 struct ion_handle *ion_hdl;
763 /*disp_mode: dual display mode
764 * NO_DUAL,no dual display,
765 ONE_DUAL,use one lcdc + rk61x for dual display
766 DUAL,use 2 lcdcs for dual display
767 num_fb: the total number of fb
768 num_lcdc: the total number of lcdc
774 struct rk29fb_info *mach_info;
775 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
777 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
780 #if defined(CONFIG_ION_ROCKCHIP)
781 struct ion_client *ion_client;
785 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
786 extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
787 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
788 struct rk_lcdc_win *win, int id);
789 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
790 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
791 extern int rk_fb_get_extern_screen(struct rk_screen *screen);
792 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
793 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
794 extern u32 rk_fb_get_prmry_screen_pixclock(void);
795 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
796 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
797 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
798 extern bool is_prmry_rk_lcdc_registered(void);
799 extern int rk_fb_prase_timing_dt(struct device_node *np,
800 struct rk_screen *screen);
801 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
803 extern int rk_fb_dpi_open(bool open);
804 extern int rk_fb_dpi_layer_sel(int layer_id);
805 extern int rk_fb_dpi_status(void);
807 extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
808 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
809 extern int rkfb_create_sysfs(struct fb_info *fbi);
810 extern char *get_format_string(enum data_format, char *fmt);
811 extern int support_uboot_display(void);
812 extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
813 extern int rk_get_real_fps(int time);
814 extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
815 extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
817 int rk_fb_get_display_policy(void);
818 int rk_fb_pixel_width(int data_format);
819 void trace_buffer_dump(struct device *dev,
820 struct rk_lcdc_driver *dev_drv);
821 extern int rockchip_get_screen_type(void);