2 * Copyright (C) 2005 David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/device.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/slab.h>
21 #include <linux/kthread.h>
22 #include <linux/completion.h>
23 #include <linux/scatterlist.h>
30 * INTERFACES between SPI master-side drivers and SPI infrastructure.
31 * (There's no SPI slave support for Linux yet...)
33 extern struct bus_type spi_bus_type;
36 * struct spi_statistics - statistics for spi transfers
37 * @lock: lock protecting this structure
39 * @messages: number of spi-messages handled
40 * @transfers: number of spi_transfers handled
41 * @errors: number of errors during spi_transfer
42 * @timedout: number of timeouts during spi_transfer
44 * @spi_sync: number of times spi_sync is used
45 * @spi_sync_immediate:
46 * number of times spi_sync is executed immediately
47 * in calling context without queuing and scheduling
48 * @spi_async: number of times spi_async is used
50 * @bytes: number of bytes transferred to/from device
51 * @bytes_tx: number of bytes sent to device
52 * @bytes_rx: number of bytes received from device
54 * @transfer_bytes_histo:
55 * transfer bytes histogramm
57 struct spi_statistics {
58 spinlock_t lock; /* lock for the whole structure */
60 unsigned long messages;
61 unsigned long transfers;
63 unsigned long timedout;
65 unsigned long spi_sync;
66 unsigned long spi_sync_immediate;
67 unsigned long spi_async;
69 unsigned long long bytes;
70 unsigned long long bytes_rx;
71 unsigned long long bytes_tx;
73 #define SPI_STATISTICS_HISTO_SIZE 17
74 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
77 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
78 struct spi_transfer *xfer,
79 struct spi_master *master);
81 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
83 unsigned long flags; \
84 spin_lock_irqsave(&(stats)->lock, flags); \
85 (stats)->field += count; \
86 spin_unlock_irqrestore(&(stats)->lock, flags); \
89 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
90 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
93 * struct spi_device - Master side proxy for an SPI slave device
94 * @dev: Driver model representation of the device.
95 * @master: SPI controller used with the device.
96 * @max_speed_hz: Maximum clock rate to be used with this chip
97 * (on this board); may be changed by the device's driver.
98 * The spi_transfer.speed_hz can override this for each transfer.
99 * @chip_select: Chipselect, distinguishing chips handled by @master.
100 * @mode: The spi mode defines how data is clocked out and in.
101 * This may be changed by the device's driver.
102 * The "active low" default for chipselect mode can be overridden
103 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
104 * each word in a transfer (by specifying SPI_LSB_FIRST).
105 * @bits_per_word: Data transfers involve one or more words; word sizes
106 * like eight or 12 bits are common. In-memory wordsizes are
107 * powers of two bytes (e.g. 20 bit samples use 32 bits).
108 * This may be changed by the device's driver, or left at the
109 * default (0) indicating protocol words are eight bit bytes.
110 * The spi_transfer.bits_per_word can override this for each transfer.
111 * @irq: Negative, or the number passed to request_irq() to receive
112 * interrupts from this device.
113 * @controller_state: Controller's runtime state
114 * @controller_data: Board-specific definitions for controller, such as
115 * FIFO initialization parameters; from board_info.controller_data
116 * @modalias: Name of the driver to use with this device, or an alias
117 * for that name. This appears in the sysfs "modalias" attribute
118 * for driver coldplugging, and in uevents used for hotplugging
119 * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when
120 * when not using a GPIO line)
122 * @statistics: statistics for the spi_device
124 * A @spi_device is used to interchange data between an SPI slave
125 * (usually a discrete chip) and CPU memory.
127 * In @dev, the platform_data is used to hold information about this
128 * device that's meaningful to the device's protocol driver, but not
129 * to its controller. One example might be an identifier for a chip
130 * variant with slightly different functionality; another might be
131 * information about how this particular board wires the chip's pins.
135 struct spi_master *master;
140 #define SPI_CPHA 0x01 /* clock phase */
141 #define SPI_CPOL 0x02 /* clock polarity */
142 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
143 #define SPI_MODE_1 (0|SPI_CPHA)
144 #define SPI_MODE_2 (SPI_CPOL|0)
145 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
146 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
147 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
148 #define SPI_3WIRE 0x10 /* SI/SO signals shared */
149 #define SPI_LOOP 0x20 /* loopback mode */
150 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
151 #define SPI_READY 0x80 /* slave pulls low to pause */
152 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
153 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
154 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
155 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
157 void *controller_state;
158 void *controller_data;
159 char modalias[SPI_NAME_SIZE];
160 int cs_gpio; /* chip select gpio */
163 struct spi_statistics statistics;
166 * likely need more hooks for more protocol options affecting how
167 * the controller talks to each chip, like:
168 * - memory packing (12 bit samples into low bits, others zeroed)
170 * - drop chipselect after each word
171 * - chipselect delays
176 static inline struct spi_device *to_spi_device(struct device *dev)
178 return dev ? container_of(dev, struct spi_device, dev) : NULL;
181 /* most drivers won't need to care about device refcounting */
182 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
184 return (spi && get_device(&spi->dev)) ? spi : NULL;
187 static inline void spi_dev_put(struct spi_device *spi)
190 put_device(&spi->dev);
193 /* ctldata is for the bus_master driver's runtime state */
194 static inline void *spi_get_ctldata(struct spi_device *spi)
196 return spi->controller_state;
199 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
201 spi->controller_state = state;
204 /* device driver data */
206 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
208 dev_set_drvdata(&spi->dev, data);
211 static inline void *spi_get_drvdata(struct spi_device *spi)
213 return dev_get_drvdata(&spi->dev);
220 * struct spi_driver - Host side "protocol" driver
221 * @id_table: List of SPI devices supported by this driver
222 * @probe: Binds this driver to the spi device. Drivers can verify
223 * that the device is actually present, and may need to configure
224 * characteristics (such as bits_per_word) which weren't needed for
225 * the initial configuration done during system setup.
226 * @remove: Unbinds this driver from the spi device
227 * @shutdown: Standard shutdown callback used during system state
228 * transitions such as powerdown/halt and kexec
229 * @driver: SPI device drivers should initialize the name and owner
230 * field of this structure.
232 * This represents the kind of device driver that uses SPI messages to
233 * interact with the hardware at the other end of a SPI link. It's called
234 * a "protocol" driver because it works through messages rather than talking
235 * directly to SPI hardware (which is what the underlying SPI controller
236 * driver does to pass those messages). These protocols are defined in the
237 * specification for the device(s) supported by the driver.
239 * As a rule, those device protocols represent the lowest level interface
240 * supported by a driver, and it will support upper level interfaces too.
241 * Examples of such upper levels include frameworks like MTD, networking,
242 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
245 const struct spi_device_id *id_table;
246 int (*probe)(struct spi_device *spi);
247 int (*remove)(struct spi_device *spi);
248 void (*shutdown)(struct spi_device *spi);
249 struct device_driver driver;
252 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
254 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
257 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
260 * spi_unregister_driver - reverse effect of spi_register_driver
261 * @sdrv: the driver to unregister
264 static inline void spi_unregister_driver(struct spi_driver *sdrv)
267 driver_unregister(&sdrv->driver);
270 /* use a define to avoid include chaining to get THIS_MODULE */
271 #define spi_register_driver(driver) \
272 __spi_register_driver(THIS_MODULE, driver)
275 * module_spi_driver() - Helper macro for registering a SPI driver
276 * @__spi_driver: spi_driver struct
278 * Helper macro for SPI drivers which do not do anything special in module
279 * init/exit. This eliminates a lot of boilerplate. Each module may only
280 * use this macro once, and calling it replaces module_init() and module_exit()
282 #define module_spi_driver(__spi_driver) \
283 module_driver(__spi_driver, spi_register_driver, \
284 spi_unregister_driver)
287 * struct spi_master - interface to SPI master controller
288 * @dev: device interface to this driver
289 * @list: link with the global spi_master list
290 * @bus_num: board-specific (and often SOC-specific) identifier for a
291 * given SPI controller.
292 * @num_chipselect: chipselects are used to distinguish individual
293 * SPI slaves, and are numbered from zero to num_chipselects.
294 * each slave has a chipselect signal, but it's common that not
295 * every chipselect is connected to a slave.
296 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
297 * @mode_bits: flags understood by this controller driver
298 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
299 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
300 * supported. If set, the SPI core will reject any transfer with an
301 * unsupported bits_per_word. If not set, this value is simply ignored,
302 * and it's up to the individual driver to perform any validation.
303 * @min_speed_hz: Lowest supported transfer speed
304 * @max_speed_hz: Highest supported transfer speed
305 * @flags: other constraints relevant to this driver
306 * @bus_lock_spinlock: spinlock for SPI bus locking
307 * @bus_lock_mutex: mutex for SPI bus locking
308 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
309 * @setup: updates the device mode and clocking records used by a
310 * device's SPI controller; protocol code may call this. This
311 * must fail if an unrecognized or unsupported mode is requested.
312 * It's always safe to call this unless transfers are pending on
313 * the device whose settings are being modified.
314 * @transfer: adds a message to the controller's transfer queue.
315 * @cleanup: frees controller-specific state
316 * @can_dma: determine whether this master supports DMA
317 * @queued: whether this master is providing an internal message queue
318 * @kworker: thread struct for message pump
319 * @kworker_task: pointer to task for message pump kworker thread
320 * @pump_messages: work struct for scheduling work to the message pump
321 * @queue_lock: spinlock to syncronise access to message queue
322 * @queue: message queue
323 * @idling: the device is entering idle state
324 * @cur_msg: the currently in-flight message
325 * @cur_msg_prepared: spi_prepare_message was called for the currently
327 * @cur_msg_mapped: message has been mapped for DMA
328 * @xfer_completion: used by core transfer_one_message()
329 * @busy: message pump is busy
330 * @running: message pump is running
331 * @rt: whether this queue is set to run as a realtime task
332 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
333 * while the hardware is prepared, using the parent
334 * device for the spidev
335 * @max_dma_len: Maximum length of a DMA transfer for the device.
336 * @prepare_transfer_hardware: a message will soon arrive from the queue
337 * so the subsystem requests the driver to prepare the transfer hardware
338 * by issuing this call
339 * @transfer_one_message: the subsystem calls the driver to transfer a single
340 * message while queuing transfers that arrive in the meantime. When the
341 * driver is finished with this message, it must call
342 * spi_finalize_current_message() so the subsystem can issue the next
344 * @unprepare_transfer_hardware: there are currently no more messages on the
345 * queue so the subsystem notifies the driver that it may relax the
346 * hardware by issuing this call
347 * @set_cs: set the logic level of the chip select line. May be called
348 * from interrupt context.
349 * @prepare_message: set up the controller to transfer a single message,
350 * for example doing DMA mapping. Called from threaded
352 * @transfer_one: transfer a single spi_transfer.
353 * - return 0 if the transfer is finished,
354 * - return 1 if the transfer is still in progress. When
355 * the driver is finished with this transfer it must
356 * call spi_finalize_current_transfer() so the subsystem
357 * can issue the next transfer. Note: transfer_one and
358 * transfer_one_message are mutually exclusive; when both
359 * are set, the generic subsystem does not call your
360 * transfer_one callback.
361 * @handle_err: the subsystem calls the driver to handle an error that occurs
362 * in the generic implementation of transfer_one_message().
363 * @unprepare_message: undo any work done by prepare_message().
364 * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
365 * number. Any individual value may be -ENOENT for CS lines that
366 * are not GPIOs (driven by the SPI controller itself).
367 * @statistics: statistics for the spi_master
368 * @dma_tx: DMA transmit channel
369 * @dma_rx: DMA receive channel
370 * @dummy_rx: dummy receive buffer for full-duplex devices
371 * @dummy_tx: dummy transmit buffer for full-duplex devices
373 * Each SPI master controller can communicate with one or more @spi_device
374 * children. These make a small bus, sharing MOSI, MISO and SCK signals
375 * but not chip select signals. Each device may be configured to use a
376 * different clock rate, since those shared signals are ignored unless
377 * the chip is selected.
379 * The driver for an SPI controller manages access to those devices through
380 * a queue of spi_message transactions, copying data between CPU memory and
381 * an SPI slave device. For each such message it queues, it calls the
382 * message's completion function when the transaction completes.
387 struct list_head list;
389 /* other than negative (== assign one dynamically), bus_num is fully
390 * board-specific. usually that simplifies to being SOC-specific.
391 * example: one SOC has three SPI controllers, numbered 0..2,
392 * and one board's schematics might show it using SPI-2. software
393 * would normally use bus_num=2 for that controller.
397 /* chipselects will be integral to many controllers; some others
398 * might use board-specific GPIOs.
402 /* some SPI controllers pose alignment requirements on DMAable
403 * buffers; let protocol drivers know about these requirements.
407 /* spi_device.mode flags understood by this controller driver */
410 /* bitmask of supported bits_per_word for transfers */
411 u32 bits_per_word_mask;
412 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
413 #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
414 #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1))
416 /* limits on transfer speed */
420 /* other constraints relevant to this driver */
422 #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
423 #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */
424 #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
425 #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */
426 #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */
428 /* lock and mutex for SPI bus locking */
429 spinlock_t bus_lock_spinlock;
430 struct mutex bus_lock_mutex;
432 /* flag indicating that the SPI bus is locked for exclusive use */
435 /* Setup mode and clock, etc (spi driver may call many times).
437 * IMPORTANT: this may be called when transfers to another
438 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
439 * which could break those transfers.
441 int (*setup)(struct spi_device *spi);
443 /* bidirectional bulk transfers
445 * + The transfer() method may not sleep; its main role is
446 * just to add the message to the queue.
447 * + For now there's no remove-from-queue operation, or
448 * any other request management
449 * + To a given spi_device, message queueing is pure fifo
451 * + The master's main job is to process its message queue,
452 * selecting a chip then transferring data
453 * + If there are multiple spi_device children, the i/o queue
454 * arbitration algorithm is unspecified (round robin, fifo,
455 * priority, reservations, preemption, etc)
457 * + Chipselect stays active during the entire message
458 * (unless modified by spi_transfer.cs_change != 0).
459 * + The message transfers use clock and SPI mode parameters
460 * previously established by setup() for this device
462 int (*transfer)(struct spi_device *spi,
463 struct spi_message *mesg);
465 /* called on release() to free memory provided by spi_master */
466 void (*cleanup)(struct spi_device *spi);
469 * Used to enable core support for DMA handling, if can_dma()
470 * exists and returns true then the transfer will be mapped
471 * prior to transfer_one() being called. The driver should
472 * not modify or store xfer and dma_tx and dma_rx must be set
473 * while the device is prepared.
475 bool (*can_dma)(struct spi_master *master,
476 struct spi_device *spi,
477 struct spi_transfer *xfer);
480 * These hooks are for drivers that want to use the generic
481 * master transfer queueing mechanism. If these are used, the
482 * transfer() function above must NOT be specified by the driver.
483 * Over time we expect SPI drivers to be phased over to this API.
486 struct kthread_worker kworker;
487 struct task_struct *kworker_task;
488 struct kthread_work pump_messages;
489 spinlock_t queue_lock;
490 struct list_head queue;
491 struct spi_message *cur_msg;
496 bool auto_runtime_pm;
497 bool cur_msg_prepared;
499 struct completion xfer_completion;
502 int (*prepare_transfer_hardware)(struct spi_master *master);
503 int (*transfer_one_message)(struct spi_master *master,
504 struct spi_message *mesg);
505 int (*unprepare_transfer_hardware)(struct spi_master *master);
506 int (*prepare_message)(struct spi_master *master,
507 struct spi_message *message);
508 int (*unprepare_message)(struct spi_master *master,
509 struct spi_message *message);
512 * These hooks are for drivers that use a generic implementation
513 * of transfer_one_message() provied by the core.
515 void (*set_cs)(struct spi_device *spi, bool enable);
516 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
517 struct spi_transfer *transfer);
518 void (*handle_err)(struct spi_master *master,
519 struct spi_message *message);
521 /* gpio chip select */
525 struct spi_statistics statistics;
527 /* DMA channels for use with core dmaengine helpers */
528 struct dma_chan *dma_tx;
529 struct dma_chan *dma_rx;
531 /* dummy data for full duplex devices */
536 static inline void *spi_master_get_devdata(struct spi_master *master)
538 return dev_get_drvdata(&master->dev);
541 static inline void spi_master_set_devdata(struct spi_master *master, void *data)
543 dev_set_drvdata(&master->dev, data);
546 static inline struct spi_master *spi_master_get(struct spi_master *master)
548 if (!master || !get_device(&master->dev))
553 static inline void spi_master_put(struct spi_master *master)
556 put_device(&master->dev);
559 /* PM calls that need to be issued by the driver */
560 extern int spi_master_suspend(struct spi_master *master);
561 extern int spi_master_resume(struct spi_master *master);
563 /* Calls the driver make to interact with the message queue */
564 extern struct spi_message *spi_get_next_queued_message(struct spi_master *master);
565 extern void spi_finalize_current_message(struct spi_master *master);
566 extern void spi_finalize_current_transfer(struct spi_master *master);
568 /* the spi driver core manages memory for the spi_master classdev */
569 extern struct spi_master *
570 spi_alloc_master(struct device *host, unsigned size);
572 extern int spi_register_master(struct spi_master *master);
573 extern int devm_spi_register_master(struct device *dev,
574 struct spi_master *master);
575 extern void spi_unregister_master(struct spi_master *master);
577 extern struct spi_master *spi_busnum_to_master(u16 busnum);
579 /*---------------------------------------------------------------------------*/
582 * I/O INTERFACE between SPI controller and protocol drivers
584 * Protocol drivers use a queue of spi_messages, each transferring data
585 * between the controller and memory buffers.
587 * The spi_messages themselves consist of a series of read+write transfer
588 * segments. Those segments always read the same number of bits as they
589 * write; but one or the other is easily ignored by passing a null buffer
590 * pointer. (This is unlike most types of I/O API, because SPI hardware
593 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
594 * up to the protocol driver, which guarantees the integrity of both (as
595 * well as the data buffers) for as long as the message is queued.
599 * struct spi_transfer - a read/write buffer pair
600 * @tx_buf: data to be written (dma-safe memory), or NULL
601 * @rx_buf: data to be read (dma-safe memory), or NULL
602 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
603 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
604 * @tx_nbits: number of bits used for writing. If 0 the default
605 * (SPI_NBITS_SINGLE) is used.
606 * @rx_nbits: number of bits used for reading. If 0 the default
607 * (SPI_NBITS_SINGLE) is used.
608 * @len: size of rx and tx buffers (in bytes)
609 * @speed_hz: Select a speed other than the device default for this
610 * transfer. If 0 the default (from @spi_device) is used.
611 * @bits_per_word: select a bits_per_word other than the device default
612 * for this transfer. If 0 the default (from @spi_device) is used.
613 * @cs_change: affects chipselect after this transfer completes
614 * @delay_usecs: microseconds to delay after this transfer before
615 * (optionally) changing the chipselect status, then starting
616 * the next transfer or completing this @spi_message.
617 * @transfer_list: transfers are sequenced through @spi_message.transfers
618 * @tx_sg: Scatterlist for transmit, currently not for client use
619 * @rx_sg: Scatterlist for receive, currently not for client use
621 * SPI transfers always write the same number of bytes as they read.
622 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
623 * In some cases, they may also want to provide DMA addresses for
624 * the data being transferred; that may reduce overhead, when the
625 * underlying driver uses dma.
627 * If the transmit buffer is null, zeroes will be shifted out
628 * while filling @rx_buf. If the receive buffer is null, the data
629 * shifted in will be discarded. Only "len" bytes shift out (or in).
630 * It's an error to try to shift out a partial word. (For example, by
631 * shifting out three bytes with word size of sixteen or twenty bits;
632 * the former uses two bytes per word, the latter uses four bytes.)
634 * In-memory data values are always in native CPU byte order, translated
635 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
636 * for example when bits_per_word is sixteen, buffers are 2N bytes long
637 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
639 * When the word size of the SPI transfer is not a power-of-two multiple
640 * of eight bits, those in-memory words include extra bits. In-memory
641 * words are always seen by protocol drivers as right-justified, so the
642 * undefined (rx) or unused (tx) bits are always the most significant bits.
644 * All SPI transfers start with the relevant chipselect active. Normally
645 * it stays selected until after the last transfer in a message. Drivers
646 * can affect the chipselect signal using cs_change.
648 * (i) If the transfer isn't the last one in the message, this flag is
649 * used to make the chipselect briefly go inactive in the middle of the
650 * message. Toggling chipselect in this way may be needed to terminate
651 * a chip command, letting a single spi_message perform all of group of
652 * chip transactions together.
654 * (ii) When the transfer is the last one in the message, the chip may
655 * stay selected until the next transfer. On multi-device SPI busses
656 * with nothing blocking messages going to other devices, this is just
657 * a performance hint; starting a message to another device deselects
658 * this one. But in other cases, this can be used to ensure correctness.
659 * Some devices need protocol transactions to be built from a series of
660 * spi_message submissions, where the content of one message is determined
661 * by the results of previous messages and where the whole transaction
662 * ends when the chipselect goes intactive.
664 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
665 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
666 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
667 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
669 * The code that submits an spi_message (and its spi_transfers)
670 * to the lower layers is responsible for managing its memory.
671 * Zero-initialize every field you don't set up explicitly, to
672 * insulate against future API updates. After you submit a message
673 * and its transfers, ignore them until its completion callback.
675 struct spi_transfer {
676 /* it's ok if tx_buf == rx_buf (right?)
677 * for MicroWire, one buffer must be null
678 * buffers must work with dma_*map_single() calls, unless
679 * spi_message.is_dma_mapped reports a pre-existing mapping
687 struct sg_table tx_sg;
688 struct sg_table rx_sg;
690 unsigned cs_change:1;
693 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
694 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
695 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
700 struct list_head transfer_list;
704 * struct spi_message - one multi-segment SPI transaction
705 * @transfers: list of transfer segments in this transaction
706 * @spi: SPI device to which the transaction is queued
707 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
708 * addresses for each transfer buffer
709 * @complete: called to report transaction completions
710 * @context: the argument to complete() when it's called
711 * @frame_length: the total number of bytes in the message
712 * @actual_length: the total number of bytes that were transferred in all
713 * successful segments
714 * @status: zero for success, else negative errno
715 * @queue: for use by whichever driver currently owns the message
716 * @state: for use by whichever driver currently owns the message
718 * A @spi_message is used to execute an atomic sequence of data transfers,
719 * each represented by a struct spi_transfer. The sequence is "atomic"
720 * in the sense that no other spi_message may use that SPI bus until that
721 * sequence completes. On some systems, many such sequences can execute as
722 * as single programmed DMA transfer. On all systems, these messages are
723 * queued, and might complete after transactions to other devices. Messages
724 * sent to a given spi_device are always executed in FIFO order.
726 * The code that submits an spi_message (and its spi_transfers)
727 * to the lower layers is responsible for managing its memory.
728 * Zero-initialize every field you don't set up explicitly, to
729 * insulate against future API updates. After you submit a message
730 * and its transfers, ignore them until its completion callback.
733 struct list_head transfers;
735 struct spi_device *spi;
737 unsigned is_dma_mapped:1;
739 /* REVISIT: we might want a flag affecting the behavior of the
740 * last transfer ... allowing things like "read 16 bit length L"
741 * immediately followed by "read L bytes". Basically imposing
742 * a specific message scheduling algorithm.
744 * Some controller drivers (message-at-a-time queue processing)
745 * could provide that as their default scheduling algorithm. But
746 * others (with multi-message pipelines) could need a flag to
747 * tell them about such special cases.
750 /* completion is reported through a callback */
751 void (*complete)(void *context);
753 unsigned frame_length;
754 unsigned actual_length;
757 /* for optional use by whatever driver currently owns the
758 * spi_message ... between calls to spi_async and then later
759 * complete(), that's the spi_master controller driver.
761 struct list_head queue;
765 static inline void spi_message_init(struct spi_message *m)
767 memset(m, 0, sizeof *m);
768 INIT_LIST_HEAD(&m->transfers);
772 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
774 list_add_tail(&t->transfer_list, &m->transfers);
778 spi_transfer_del(struct spi_transfer *t)
780 list_del(&t->transfer_list);
784 * spi_message_init_with_transfers - Initialize spi_message and append transfers
785 * @m: spi_message to be initialized
786 * @xfers: An array of spi transfers
787 * @num_xfers: Number of items in the xfer array
789 * This function initializes the given spi_message and adds each spi_transfer in
790 * the given array to the message.
793 spi_message_init_with_transfers(struct spi_message *m,
794 struct spi_transfer *xfers, unsigned int num_xfers)
799 for (i = 0; i < num_xfers; ++i)
800 spi_message_add_tail(&xfers[i], m);
803 /* It's fine to embed message and transaction structures in other data
804 * structures so long as you don't free them while they're in use.
807 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
809 struct spi_message *m;
811 m = kzalloc(sizeof(struct spi_message)
812 + ntrans * sizeof(struct spi_transfer),
816 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
818 INIT_LIST_HEAD(&m->transfers);
819 for (i = 0; i < ntrans; i++, t++)
820 spi_message_add_tail(t, m);
825 static inline void spi_message_free(struct spi_message *m)
830 extern int spi_setup(struct spi_device *spi);
831 extern int spi_async(struct spi_device *spi, struct spi_message *message);
832 extern int spi_async_locked(struct spi_device *spi,
833 struct spi_message *message);
835 /*---------------------------------------------------------------------------*/
837 /* All these synchronous SPI transfer routines are utilities layered
838 * over the core async transfer primitive. Here, "synchronous" means
839 * they will sleep uninterruptibly until the async transfer completes.
842 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
843 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
844 extern int spi_bus_lock(struct spi_master *master);
845 extern int spi_bus_unlock(struct spi_master *master);
848 * spi_write - SPI synchronous write
849 * @spi: device to which data will be written
851 * @len: data buffer size
854 * This function writes the buffer @buf.
855 * Callable only from contexts that can sleep.
857 * Return: zero on success, else a negative error code.
860 spi_write(struct spi_device *spi, const void *buf, size_t len)
862 struct spi_transfer t = {
866 struct spi_message m;
868 spi_message_init(&m);
869 spi_message_add_tail(&t, &m);
870 return spi_sync(spi, &m);
874 * spi_read - SPI synchronous read
875 * @spi: device from which data will be read
877 * @len: data buffer size
880 * This function reads the buffer @buf.
881 * Callable only from contexts that can sleep.
883 * Return: zero on success, else a negative error code.
886 spi_read(struct spi_device *spi, void *buf, size_t len)
888 struct spi_transfer t = {
892 struct spi_message m;
894 spi_message_init(&m);
895 spi_message_add_tail(&t, &m);
896 return spi_sync(spi, &m);
900 * spi_sync_transfer - synchronous SPI data transfer
901 * @spi: device with which data will be exchanged
902 * @xfers: An array of spi_transfers
903 * @num_xfers: Number of items in the xfer array
906 * Does a synchronous SPI data transfer of the given spi_transfer array.
908 * For more specific semantics see spi_sync().
910 * Return: Return: zero on success, else a negative error code.
913 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
914 unsigned int num_xfers)
916 struct spi_message msg;
918 spi_message_init_with_transfers(&msg, xfers, num_xfers);
920 return spi_sync(spi, &msg);
923 /* this copies txbuf and rxbuf data; for small transfers only! */
924 extern int spi_write_then_read(struct spi_device *spi,
925 const void *txbuf, unsigned n_tx,
926 void *rxbuf, unsigned n_rx);
929 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
930 * @spi: device with which data will be exchanged
931 * @cmd: command to be written before data is read back
934 * Callable only from contexts that can sleep.
936 * Return: the (unsigned) eight bit number returned by the
937 * device, or else a negative error code.
939 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
944 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
946 /* return negative errno or unsigned value */
947 return (status < 0) ? status : result;
951 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
952 * @spi: device with which data will be exchanged
953 * @cmd: command to be written before data is read back
956 * The number is returned in wire-order, which is at least sometimes
959 * Callable only from contexts that can sleep.
961 * Return: the (unsigned) sixteen bit number returned by the
962 * device, or else a negative error code.
964 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
969 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
971 /* return negative errno or unsigned value */
972 return (status < 0) ? status : result;
976 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
977 * @spi: device with which data will be exchanged
978 * @cmd: command to be written before data is read back
981 * This function is similar to spi_w8r16, with the exception that it will
982 * convert the read 16 bit data word from big-endian to native endianness.
984 * Callable only from contexts that can sleep.
986 * Return: the (unsigned) sixteen bit number returned by the device in cpu
987 * endianness, or else a negative error code.
989 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
995 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
999 return be16_to_cpu(result);
1002 /*---------------------------------------------------------------------------*/
1005 * INTERFACE between board init code and SPI infrastructure.
1007 * No SPI driver ever sees these SPI device table segments, but
1008 * it's how the SPI core (or adapters that get hotplugged) grows
1009 * the driver model tree.
1011 * As a rule, SPI devices can't be probed. Instead, board init code
1012 * provides a table listing the devices which are present, with enough
1013 * information to bind and set up the device's driver. There's basic
1014 * support for nonstatic configurations too; enough to handle adding
1015 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1019 * struct spi_board_info - board-specific template for a SPI device
1020 * @modalias: Initializes spi_device.modalias; identifies the driver.
1021 * @platform_data: Initializes spi_device.platform_data; the particular
1022 * data stored there is driver-specific.
1023 * @controller_data: Initializes spi_device.controller_data; some
1024 * controllers need hints about hardware setup, e.g. for DMA.
1025 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1026 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1027 * from the chip datasheet and board-specific signal quality issues.
1028 * @bus_num: Identifies which spi_master parents the spi_device; unused
1029 * by spi_new_device(), and otherwise depends on board wiring.
1030 * @chip_select: Initializes spi_device.chip_select; depends on how
1031 * the board is wired.
1032 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1033 * wiring (some devices support both 3WIRE and standard modes), and
1034 * possibly presence of an inverter in the chipselect path.
1036 * When adding new SPI devices to the device tree, these structures serve
1037 * as a partial device template. They hold information which can't always
1038 * be determined by drivers. Information that probe() can establish (such
1039 * as the default transfer wordsize) is not included here.
1041 * These structures are used in two places. Their primary role is to
1042 * be stored in tables of board-specific device descriptors, which are
1043 * declared early in board initialization and then used (much later) to
1044 * populate a controller's device tree after the that controller's driver
1045 * initializes. A secondary (and atypical) role is as a parameter to
1046 * spi_new_device() call, which happens after those controller drivers
1047 * are active in some dynamic board configuration models.
1049 struct spi_board_info {
1050 /* the device name and module name are coupled, like platform_bus;
1051 * "modalias" is normally the driver name.
1053 * platform_data goes to spi_device.dev.platform_data,
1054 * controller_data goes to spi_device.controller_data,
1057 char modalias[SPI_NAME_SIZE];
1058 const void *platform_data;
1059 void *controller_data;
1062 /* slower signaling on noisy or low voltage boards */
1066 /* bus_num is board specific and matches the bus_num of some
1067 * spi_master that will probably be registered later.
1069 * chip_select reflects how this chip is wired to that master;
1070 * it's less than num_chipselect.
1075 /* mode becomes spi_device.mode, and is essential for chips
1076 * where the default of SPI_CS_HIGH = 0 is wrong.
1080 /* ... may need additional spi_device chip config data here.
1081 * avoid stuff protocol drivers can set; but include stuff
1082 * needed to behave without being bound to a driver:
1083 * - quirks like clock rate mattering when not selected
1089 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1091 /* board init code may ignore whether SPI is configured or not */
1093 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1098 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1099 * use spi_new_device() to describe each device. You can also call
1100 * spi_unregister_device() to start making that device vanish, but
1101 * normally that would be handled by spi_unregister_master().
1103 * You can also use spi_alloc_device() and spi_add_device() to use a two
1104 * stage registration sequence for each spi_device. This gives the caller
1105 * some more control over the spi_device structure before it is registered,
1106 * but requires that caller to initialize fields that would otherwise
1107 * be defined using the board info.
1109 extern struct spi_device *
1110 spi_alloc_device(struct spi_master *master);
1113 spi_add_device(struct spi_device *spi);
1115 extern struct spi_device *
1116 spi_new_device(struct spi_master *, struct spi_board_info *);
1119 spi_unregister_device(struct spi_device *spi)
1122 device_unregister(&spi->dev);
1125 extern const struct spi_device_id *
1126 spi_get_device_id(const struct spi_device *sdev);
1129 spi_transfer_is_last(struct spi_master *master, struct spi_transfer *xfer)
1131 return list_is_last(&xfer->transfer_list, &master->cur_msg->transfers);
1134 #endif /* __LINUX_SPI_H */