1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineBasicBlock;
29 class MachineConstantPool;
30 class MachineFunction;
32 class MachineFrameInfo;
33 class MachineRegisterInfo;
35 class TargetInstrInfo;
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
41 /// FastISel - This is a fast-path instruction selection class that
42 /// generates poor code and doesn't support illegal types or non-trivial
43 /// lowering, but runs quickly.
46 MachineBasicBlock *MBB;
47 DenseMap<const Value *, unsigned> LocalValueMap;
48 DenseMap<const Value *, unsigned> &ValueMap;
49 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
50 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
51 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
53 SmallSet<const Instruction *, 8> &CatchInfoLost;
56 MachineRegisterInfo &MRI;
57 MachineFrameInfo &MFI;
58 MachineConstantPool &MCP;
60 const TargetMachine &TM;
62 const TargetInstrInfo &TII;
63 const TargetLowering &TLI;
64 const TargetRegisterInfo &TRI;
68 /// startNewBlock - Set the current block to which generated machine
69 /// instructions will be appended, and clear the local CSE map.
71 void startNewBlock(MachineBasicBlock *mbb) {
73 LocalValueMap.clear();
76 /// setCurrentBlock - Set the current block to which generated machine
77 /// instructions will be appended.
79 void setCurrentBlock(MachineBasicBlock *mbb) {
83 /// getCurDebugLoc() - Return current debug location information.
84 DebugLoc getCurDebugLoc() const { return DL; }
86 /// SelectInstruction - Do "fast" instruction selection for the given
87 /// LLVM IR instruction, and append generated machine instructions to
88 /// the current block. Return true if selection was successful.
90 bool SelectInstruction(const Instruction *I);
92 /// SelectOperator - Do "fast" instruction selection for the given
93 /// LLVM IR operator (Instruction or ConstantExpr), and append
94 /// generated machine instructions to the current block. Return true
95 /// if selection was successful.
97 bool SelectOperator(const User *I, unsigned Opcode);
99 /// getRegForValue - Create a virtual register and arrange for it to
100 /// be assigned the value for the given LLVM value.
101 unsigned getRegForValue(const Value *V);
103 /// lookUpRegForValue - Look up the value to see if its value is already
104 /// cached in a register. It may be defined by instructions across blocks or
106 unsigned lookUpRegForValue(const Value *V);
108 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
109 /// takes care of truncating or sign-extending the given getelementptr
111 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
116 FastISel(MachineFunction &mf,
117 DenseMap<const Value *, unsigned> &vm,
118 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
119 DenseMap<const AllocaInst *, int> &am,
120 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
122 , SmallSet<const Instruction *, 8> &cil
126 /// TargetSelectInstruction - This method is called by target-independent
127 /// code when the normal FastISel process fails to select an instruction.
128 /// This gives targets a chance to emit code for anything that doesn't
129 /// fit into FastISel's framework. It returns true if it was successful.
132 TargetSelectInstruction(const Instruction *I) = 0;
134 /// FastEmit_r - This method is called by target-independent code
135 /// to request that an instruction with the given type and opcode
137 virtual unsigned FastEmit_(MVT VT,
141 /// FastEmit_r - This method is called by target-independent code
142 /// to request that an instruction with the given type, opcode, and
143 /// register operand be emitted.
145 virtual unsigned FastEmit_r(MVT VT,
148 unsigned Op0, bool Op0IsKill);
150 /// FastEmit_rr - This method is called by target-independent code
151 /// to request that an instruction with the given type, opcode, and
152 /// register operands be emitted.
154 virtual unsigned FastEmit_rr(MVT VT,
157 unsigned Op0, bool Op0IsKill,
158 unsigned Op1, bool Op1IsKill);
160 /// FastEmit_ri - This method is called by target-independent code
161 /// to request that an instruction with the given type, opcode, and
162 /// register and immediate operands be emitted.
164 virtual unsigned FastEmit_ri(MVT VT,
167 unsigned Op0, bool Op0IsKill,
170 /// FastEmit_rf - This method is called by target-independent code
171 /// to request that an instruction with the given type, opcode, and
172 /// register and floating-point immediate operands be emitted.
174 virtual unsigned FastEmit_rf(MVT VT,
177 unsigned Op0, bool Op0IsKill,
178 const ConstantFP *FPImm);
180 /// FastEmit_rri - This method is called by target-independent code
181 /// to request that an instruction with the given type, opcode, and
182 /// register and immediate operands be emitted.
184 virtual unsigned FastEmit_rri(MVT VT,
187 unsigned Op0, bool Op0IsKill,
188 unsigned Op1, bool Op1IsKill,
191 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
192 /// to emit an instruction with an immediate operand using FastEmit_ri.
193 /// If that fails, it materializes the immediate into a register and try
194 /// FastEmit_rr instead.
195 unsigned FastEmit_ri_(MVT VT,
197 unsigned Op0, bool Op0IsKill,
198 uint64_t Imm, MVT ImmType);
200 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
201 /// to emit an instruction with an immediate operand using FastEmit_rf.
202 /// If that fails, it materializes the immediate into a register and try
203 /// FastEmit_rr instead.
204 unsigned FastEmit_rf_(MVT VT,
206 unsigned Op0, bool Op0IsKill,
207 const ConstantFP *FPImm, MVT ImmType);
209 /// FastEmit_i - This method is called by target-independent code
210 /// to request that an instruction with the given type, opcode, and
211 /// immediate operand be emitted.
212 virtual unsigned FastEmit_i(MVT VT,
217 /// FastEmit_f - This method is called by target-independent code
218 /// to request that an instruction with the given type, opcode, and
219 /// floating-point immediate operand be emitted.
220 virtual unsigned FastEmit_f(MVT VT,
223 const ConstantFP *FPImm);
225 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
226 /// result register in the given register class.
228 unsigned FastEmitInst_(unsigned MachineInstOpcode,
229 const TargetRegisterClass *RC);
231 /// FastEmitInst_r - Emit a MachineInstr with one register operand
232 /// and a result register in the given register class.
234 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
235 const TargetRegisterClass *RC,
236 unsigned Op0, bool Op0IsKill);
238 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
239 /// and a result register in the given register class.
241 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
242 const TargetRegisterClass *RC,
243 unsigned Op0, bool Op0IsKill,
244 unsigned Op1, bool Op1IsKill);
246 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
247 /// and a result register in the given register class.
249 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
250 const TargetRegisterClass *RC,
251 unsigned Op0, bool Op0IsKill,
254 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
255 /// and a result register in the given register class.
257 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
258 const TargetRegisterClass *RC,
259 unsigned Op0, bool Op0IsKill,
260 const ConstantFP *FPImm);
262 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
263 /// an immediate, and a result register in the given register class.
265 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
266 const TargetRegisterClass *RC,
267 unsigned Op0, bool Op0IsKill,
268 unsigned Op1, bool Op1IsKill,
271 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
272 /// operand, and a result register in the given register class.
273 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
274 const TargetRegisterClass *RC,
277 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
278 /// from a specified index of a superregister to a specified type.
279 unsigned FastEmitInst_extractsubreg(MVT RetVT,
280 unsigned Op0, bool Op0IsKill,
283 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
284 /// with all but the least significant bit set to zero.
285 unsigned FastEmitZExtFromI1(MVT VT,
286 unsigned Op0, bool Op0IsKill);
288 /// FastEmitBranch - Emit an unconditional branch to the given block,
289 /// unless it is the immediate (fall-through) successor, and update
291 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
293 unsigned UpdateValueMap(const Value* I, unsigned Reg);
295 unsigned createResultReg(const TargetRegisterClass *RC);
297 /// TargetMaterializeConstant - Emit a constant in a register using
298 /// target-specific logic, such as constant pool loads.
299 virtual unsigned TargetMaterializeConstant(const Constant* C) {
303 /// TargetMaterializeAlloca - Emit an alloca address in a register using
304 /// target-specific logic.
305 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
310 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
312 bool SelectFNeg(const User *I);
314 bool SelectGetElementPtr(const User *I);
316 bool SelectCall(const User *I);
318 bool SelectBitCast(const User *I);
320 bool SelectCast(const User *I, unsigned Opcode);
322 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
323 /// Emit code to ensure constants are copied into registers when needed.
324 /// Remember the virtual registers that need to be added to the Machine PHI
325 /// nodes as input. We cannot just directly add them, because expansion
326 /// might result in multiple MBB's for one BB. As such, the start of the
327 /// BB might correspond to a different MBB than the end.
328 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
330 /// materializeRegForValue - Helper for getRegForVale. This function is
331 /// called when the value isn't already available in a register and must
332 /// be materialized with new instructions.
333 unsigned materializeRegForValue(const Value *V, MVT VT);
335 /// hasTrivialKill - Test whether the given value has exactly one use.
336 bool hasTrivialKill(const Value *V) const;