1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
25 class FunctionLoweringInfo;
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
31 class MachineFrameInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
41 /// FastISel - This is a fast-path instruction selection class that
42 /// generates poor code and doesn't support illegal types or non-trivial
43 /// lowering, but runs quickly.
46 DenseMap<const Value *, unsigned> LocalValueMap;
47 FunctionLoweringInfo &FuncInfo;
48 MachineRegisterInfo &MRI;
49 MachineFrameInfo &MFI;
50 MachineConstantPool &MCP;
52 const TargetMachine &TM;
54 const TargetInstrInfo &TII;
55 const TargetLowering &TLI;
56 const TargetRegisterInfo &TRI;
57 MachineInstr *LastLocalValue;
60 /// getLastLocalValue - Return the position of the last instruction
61 /// emitted for materializing constants for use in the current block.
62 MachineInstr *getLastLocalValue() { return LastLocalValue; }
64 /// setLastLocalValue - Update the position of the last instruction
65 /// emitted for materializing constants for use in the current block.
66 void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
68 /// startNewBlock - Set the current block to which generated machine
69 /// instructions will be appended, and clear the local CSE map.
73 /// getCurDebugLoc() - Return current debug location information.
74 DebugLoc getCurDebugLoc() const { return DL; }
76 /// SelectInstruction - Do "fast" instruction selection for the given
77 /// LLVM IR instruction, and append generated machine instructions to
78 /// the current block. Return true if selection was successful.
80 bool SelectInstruction(const Instruction *I);
82 /// SelectOperator - Do "fast" instruction selection for the given
83 /// LLVM IR operator (Instruction or ConstantExpr), and append
84 /// generated machine instructions to the current block. Return true
85 /// if selection was successful.
87 bool SelectOperator(const User *I, unsigned Opcode);
89 /// getRegForValue - Create a virtual register and arrange for it to
90 /// be assigned the value for the given LLVM value.
91 unsigned getRegForValue(const Value *V);
93 /// lookUpRegForValue - Look up the value to see if its value is already
94 /// cached in a register. It may be defined by instructions across blocks or
96 unsigned lookUpRegForValue(const Value *V);
98 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
99 /// takes care of truncating or sign-extending the given getelementptr
101 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
103 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
104 /// vreg is being provided by the specified load instruction. If possible,
105 /// try to fold the load as an operand to the instruction, returning true if
107 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/,
108 const LoadInst * /*LI*/) {
112 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
113 /// into the current block.
114 void recomputeInsertPt();
117 MachineBasicBlock::iterator InsertPt;
121 /// recomputeDebugLocForMaterializedRegs - Recompute debug location for
122 /// very first instruction in a basic block.
123 void recomputeDebugLocForMaterializedRegs();
125 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
126 /// into the local value area and return the old insert position.
127 SavePoint enterLocalValueArea();
129 /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
130 void leaveLocalValueArea(SavePoint Old);
135 explicit FastISel(FunctionLoweringInfo &funcInfo);
137 /// TargetSelectInstruction - This method is called by target-independent
138 /// code when the normal FastISel process fails to select an instruction.
139 /// This gives targets a chance to emit code for anything that doesn't
140 /// fit into FastISel's framework. It returns true if it was successful.
143 TargetSelectInstruction(const Instruction *I) = 0;
145 /// FastEmit_r - This method is called by target-independent code
146 /// to request that an instruction with the given type and opcode
148 virtual unsigned FastEmit_(MVT VT,
152 /// FastEmit_r - This method is called by target-independent code
153 /// to request that an instruction with the given type, opcode, and
154 /// register operand be emitted.
156 virtual unsigned FastEmit_r(MVT VT,
159 unsigned Op0, bool Op0IsKill);
161 /// FastEmit_rr - This method is called by target-independent code
162 /// to request that an instruction with the given type, opcode, and
163 /// register operands be emitted.
165 virtual unsigned FastEmit_rr(MVT VT,
168 unsigned Op0, bool Op0IsKill,
169 unsigned Op1, bool Op1IsKill);
171 /// FastEmit_ri - This method is called by target-independent code
172 /// to request that an instruction with the given type, opcode, and
173 /// register and immediate operands be emitted.
175 virtual unsigned FastEmit_ri(MVT VT,
178 unsigned Op0, bool Op0IsKill,
181 /// FastEmit_rf - This method is called by target-independent code
182 /// to request that an instruction with the given type, opcode, and
183 /// register and floating-point immediate operands be emitted.
185 virtual unsigned FastEmit_rf(MVT VT,
188 unsigned Op0, bool Op0IsKill,
189 const ConstantFP *FPImm);
191 /// FastEmit_rri - This method is called by target-independent code
192 /// to request that an instruction with the given type, opcode, and
193 /// register and immediate operands be emitted.
195 virtual unsigned FastEmit_rri(MVT VT,
198 unsigned Op0, bool Op0IsKill,
199 unsigned Op1, bool Op1IsKill,
202 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
203 /// to emit an instruction with an immediate operand using FastEmit_ri.
204 /// If that fails, it materializes the immediate into a register and try
205 /// FastEmit_rr instead.
206 unsigned FastEmit_ri_(MVT VT,
208 unsigned Op0, bool Op0IsKill,
209 uint64_t Imm, MVT ImmType);
211 /// FastEmit_i - This method is called by target-independent code
212 /// to request that an instruction with the given type, opcode, and
213 /// immediate operand be emitted.
214 virtual unsigned FastEmit_i(MVT VT,
219 /// FastEmit_f - This method is called by target-independent code
220 /// to request that an instruction with the given type, opcode, and
221 /// floating-point immediate operand be emitted.
222 virtual unsigned FastEmit_f(MVT VT,
225 const ConstantFP *FPImm);
227 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
228 /// result register in the given register class.
230 unsigned FastEmitInst_(unsigned MachineInstOpcode,
231 const TargetRegisterClass *RC);
233 /// FastEmitInst_r - Emit a MachineInstr with one register operand
234 /// and a result register in the given register class.
236 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
237 const TargetRegisterClass *RC,
238 unsigned Op0, bool Op0IsKill);
240 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
241 /// and a result register in the given register class.
243 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
244 const TargetRegisterClass *RC,
245 unsigned Op0, bool Op0IsKill,
246 unsigned Op1, bool Op1IsKill);
248 /// FastEmitInst_rrr - Emit a MachineInstr with three register operands
249 /// and a result register in the given register class.
251 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
252 const TargetRegisterClass *RC,
253 unsigned Op0, bool Op0IsKill,
254 unsigned Op1, bool Op1IsKill,
255 unsigned Op2, bool Op2IsKill);
257 /// FastEmitInst_ri - Emit a MachineInstr with a register operand,
258 /// an immediate, and a result register in the given register class.
260 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
261 const TargetRegisterClass *RC,
262 unsigned Op0, bool Op0IsKill,
265 /// FastEmitInst_rii - Emit a MachineInstr with one register operand
266 /// and two immediate operands.
268 unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
271 uint64_t Imm1, uint64_t Imm2);
273 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
274 /// and a result register in the given register class.
276 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
277 const TargetRegisterClass *RC,
278 unsigned Op0, bool Op0IsKill,
279 const ConstantFP *FPImm);
281 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
282 /// an immediate, and a result register in the given register class.
284 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
285 const TargetRegisterClass *RC,
286 unsigned Op0, bool Op0IsKill,
287 unsigned Op1, bool Op1IsKill,
290 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
291 /// operand, and a result register in the given register class.
292 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
293 const TargetRegisterClass *RC,
296 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
297 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
298 const TargetRegisterClass *RC,
299 uint64_t Imm1, uint64_t Imm2);
301 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
302 /// from a specified index of a superregister to a specified type.
303 unsigned FastEmitInst_extractsubreg(MVT RetVT,
304 unsigned Op0, bool Op0IsKill,
307 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
308 /// with all but the least significant bit set to zero.
309 unsigned FastEmitZExtFromI1(MVT VT,
310 unsigned Op0, bool Op0IsKill);
312 /// FastEmitBranch - Emit an unconditional branch to the given block,
313 /// unless it is the immediate (fall-through) successor, and update
315 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
317 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
319 unsigned createResultReg(const TargetRegisterClass *RC);
321 /// TargetMaterializeConstant - Emit a constant in a register using
322 /// target-specific logic, such as constant pool loads.
323 virtual unsigned TargetMaterializeConstant(const Constant* C) {
327 /// TargetMaterializeAlloca - Emit an alloca address in a register using
328 /// target-specific logic.
329 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
333 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
338 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
340 bool SelectFNeg(const User *I);
342 bool SelectGetElementPtr(const User *I);
344 bool SelectCall(const User *I);
346 bool SelectBitCast(const User *I);
348 bool SelectCast(const User *I, unsigned Opcode);
350 bool SelectExtractValue(const User *I);
352 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
353 /// Emit code to ensure constants are copied into registers when needed.
354 /// Remember the virtual registers that need to be added to the Machine PHI
355 /// nodes as input. We cannot just directly add them, because expansion
356 /// might result in multiple MBB's for one BB. As such, the start of the
357 /// BB might correspond to a different MBB than the end.
358 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
360 /// materializeRegForValue - Helper for getRegForVale. This function is
361 /// called when the value isn't already available in a register and must
362 /// be materialized with new instructions.
363 unsigned materializeRegForValue(const Value *V, MVT VT);
365 /// hasTrivialKill - Test whether the given value has exactly one use.
366 bool hasTrivialKill(const Value *V) const;