1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineFrameInfo;
31 class MachineModuleInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
39 /// FastISel - This is a fast-path instruction selection class that
40 /// generates poor code and doesn't support illegal types or non-trivial
41 /// lowering, but runs quickly.
44 MachineBasicBlock *MBB;
45 DenseMap<const Value *, unsigned> LocalValueMap;
46 DenseMap<const Value *, unsigned> &ValueMap;
47 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 SmallSet<Instruction*, 8> &CatchInfoLost;
53 MachineModuleInfo *MMI;
54 MachineRegisterInfo &MRI;
55 MachineFrameInfo &MFI;
56 MachineConstantPool &MCP;
57 const TargetMachine &TM;
59 const TargetInstrInfo &TII;
60 const TargetLowering &TLI;
63 /// startNewBlock - Set the current block, to which generated
64 /// machine instructions will be appended, and clear the local
67 void startNewBlock(MachineBasicBlock *mbb) {
69 LocalValueMap.clear();
72 /// setCurrentBlock - Set the current block, to which generated
73 /// machine instructions will be appended.
75 void setCurrentBlock(MachineBasicBlock *mbb) {
79 /// SelectInstruction - Do "fast" instruction selection for the given
80 /// LLVM IR instruction, and append generated machine instructions to
81 /// the current block. Return true if selection was successful.
83 bool SelectInstruction(Instruction *I);
85 /// SelectInstruction - Do "fast" instruction selection for the given
86 /// LLVM IR operator (Instruction or ConstantExpr), and append
87 /// generated machine instructions to the current block. Return true
88 /// if selection was successful.
90 bool SelectOperator(User *I, unsigned Opcode);
92 /// TargetSelectInstruction - This method is called by target-independent
93 /// code when the normal FastISel process fails to select an instruction.
94 /// This gives targets a chance to emit code for anything that doesn't
95 /// fit into FastISel's framework. It returns true if it was successful.
98 TargetSelectInstruction(Instruction *I) = 0;
100 /// getRegForValue - Create a virtual register and arrange for it to
101 /// be assigned the value for the given LLVM value.
102 unsigned getRegForValue(Value *V);
104 /// lookUpRegForValue - Look up the value to see if its value is already
105 /// cached in a register. It may be defined by instructions across blocks or
107 unsigned lookUpRegForValue(Value *V);
109 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
110 /// takes care of truncating or sign-extending the given getelementptr
112 unsigned getRegForGEPIndex(Value *V);
117 FastISel(MachineFunction &mf,
118 MachineModuleInfo *mmi,
119 DenseMap<const Value *, unsigned> &vm,
120 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
121 DenseMap<const AllocaInst *, int> &am
123 , SmallSet<Instruction*, 8> &cil
127 /// FastEmit_r - This method is called by target-independent code
128 /// to request that an instruction with the given type and opcode
130 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
131 MVT::SimpleValueType RetVT,
132 ISD::NodeType Opcode);
134 /// FastEmit_r - This method is called by target-independent code
135 /// to request that an instruction with the given type, opcode, and
136 /// register operand be emitted.
138 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
139 MVT::SimpleValueType RetVT,
140 ISD::NodeType Opcode, unsigned Op0);
142 /// FastEmit_rr - This method is called by target-independent code
143 /// to request that an instruction with the given type, opcode, and
144 /// register operands be emitted.
146 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
147 MVT::SimpleValueType RetVT,
148 ISD::NodeType Opcode,
149 unsigned Op0, unsigned Op1);
151 /// FastEmit_ri - This method is called by target-independent code
152 /// to request that an instruction with the given type, opcode, and
153 /// register and immediate operands be emitted.
155 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
156 MVT::SimpleValueType RetVT,
157 ISD::NodeType Opcode,
158 unsigned Op0, uint64_t Imm);
160 /// FastEmit_rf - This method is called by target-independent code
161 /// to request that an instruction with the given type, opcode, and
162 /// register and floating-point immediate operands be emitted.
164 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
165 MVT::SimpleValueType RetVT,
166 ISD::NodeType Opcode,
167 unsigned Op0, ConstantFP *FPImm);
169 /// FastEmit_rri - This method is called by target-independent code
170 /// to request that an instruction with the given type, opcode, and
171 /// register and immediate operands be emitted.
173 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
174 MVT::SimpleValueType RetVT,
175 ISD::NodeType Opcode,
176 unsigned Op0, unsigned Op1, uint64_t Imm);
178 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
179 /// to emit an instruction with an immediate operand using FastEmit_ri.
180 /// If that fails, it materializes the immediate into a register and try
181 /// FastEmit_rr instead.
182 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
183 ISD::NodeType Opcode,
184 unsigned Op0, uint64_t Imm,
185 MVT::SimpleValueType ImmType);
187 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
188 /// to emit an instruction with an immediate operand using FastEmit_rf.
189 /// If that fails, it materializes the immediate into a register and try
190 /// FastEmit_rr instead.
191 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
192 ISD::NodeType Opcode,
193 unsigned Op0, ConstantFP *FPImm,
194 MVT::SimpleValueType ImmType);
196 /// FastEmit_i - This method is called by target-independent code
197 /// to request that an instruction with the given type, opcode, and
198 /// immediate operand be emitted.
199 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
200 MVT::SimpleValueType RetVT,
201 ISD::NodeType Opcode,
204 /// FastEmit_f - This method is called by target-independent code
205 /// to request that an instruction with the given type, opcode, and
206 /// floating-point immediate operand be emitted.
207 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
208 MVT::SimpleValueType RetVT,
209 ISD::NodeType Opcode,
212 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
213 /// result register in the given register class.
215 unsigned FastEmitInst_(unsigned MachineInstOpcode,
216 const TargetRegisterClass *RC);
218 /// FastEmitInst_r - Emit a MachineInstr with one register operand
219 /// and a result register in the given register class.
221 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
222 const TargetRegisterClass *RC,
225 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
226 /// and a result register in the given register class.
228 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
229 const TargetRegisterClass *RC,
230 unsigned Op0, unsigned Op1);
232 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
233 /// and a result register in the given register class.
235 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC,
237 unsigned Op0, uint64_t Imm);
239 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
240 /// and a result register in the given register class.
242 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
243 const TargetRegisterClass *RC,
244 unsigned Op0, ConstantFP *FPImm);
246 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
247 /// an immediate, and a result register in the given register class.
249 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
250 const TargetRegisterClass *RC,
251 unsigned Op0, unsigned Op1, uint64_t Imm);
253 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
254 /// operand, and a result register in the given register class.
255 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
256 const TargetRegisterClass *RC,
259 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
260 /// from a specified index of a superregister.
261 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
263 /// FastEmitBranch - Emit an unconditional branch to the given block,
264 /// unless it is the immediate (fall-through) successor, and update
266 void FastEmitBranch(MachineBasicBlock *MBB);
268 void UpdateValueMap(Value* I, unsigned Reg);
270 unsigned createResultReg(const TargetRegisterClass *RC);
272 /// TargetMaterializeConstant - Emit a constant in a register using
273 /// target-specific logic, such as constant pool loads.
274 virtual unsigned TargetMaterializeConstant(Constant* C) {
278 /// TargetMaterializeAlloca - Emit an alloca address in a register using
279 /// target-specific logic.
280 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
285 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
287 bool SelectGetElementPtr(User *I);
289 bool SelectCall(User *I);
291 bool SelectBitCast(User *I);
293 bool SelectCast(User *I, ISD::NodeType Opcode);