1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineBasicBlock;
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineFrameInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
39 /// FastISel - This is a fast-path instruction selection class that
40 /// generates poor code and doesn't support illegal types or non-trivial
41 /// lowering, but runs quickly.
44 MachineBasicBlock *MBB;
45 DenseMap<const Value *, unsigned> LocalValueMap;
46 DenseMap<const Value *, unsigned> &ValueMap;
47 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 SmallSet<const Instruction *, 8> &CatchInfoLost;
53 MachineRegisterInfo &MRI;
54 MachineFrameInfo &MFI;
55 MachineConstantPool &MCP;
57 const TargetMachine &TM;
59 const TargetInstrInfo &TII;
60 const TargetLowering &TLI;
63 /// startNewBlock - Set the current block to which generated machine
64 /// instructions will be appended, and clear the local CSE map.
66 void startNewBlock(MachineBasicBlock *mbb) {
68 LocalValueMap.clear();
71 /// setCurrentBlock - Set the current block to which generated machine
72 /// instructions will be appended.
74 void setCurrentBlock(MachineBasicBlock *mbb) {
78 /// getCurDebugLoc() - Return current debug location information.
79 DebugLoc getCurDebugLoc() const { return DL; }
81 /// SelectInstruction - Do "fast" instruction selection for the given
82 /// LLVM IR instruction, and append generated machine instructions to
83 /// the current block. Return true if selection was successful.
85 bool SelectInstruction(const Instruction *I);
87 /// SelectOperator - Do "fast" instruction selection for the given
88 /// LLVM IR operator (Instruction or ConstantExpr), and append
89 /// generated machine instructions to the current block. Return true
90 /// if selection was successful.
92 bool SelectOperator(const User *I, unsigned Opcode);
94 /// getRegForValue - Create a virtual register and arrange for it to
95 /// be assigned the value for the given LLVM value.
96 unsigned getRegForValue(const Value *V);
98 /// lookUpRegForValue - Look up the value to see if its value is already
99 /// cached in a register. It may be defined by instructions across blocks or
101 unsigned lookUpRegForValue(const Value *V);
103 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
104 /// takes care of truncating or sign-extending the given getelementptr
106 unsigned getRegForGEPIndex(const Value *V);
111 FastISel(MachineFunction &mf,
112 DenseMap<const Value *, unsigned> &vm,
113 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
114 DenseMap<const AllocaInst *, int> &am
116 , SmallSet<const Instruction *, 8> &cil
120 /// TargetSelectInstruction - This method is called by target-independent
121 /// code when the normal FastISel process fails to select an instruction.
122 /// This gives targets a chance to emit code for anything that doesn't
123 /// fit into FastISel's framework. It returns true if it was successful.
126 TargetSelectInstruction(const Instruction *I) = 0;
128 /// FastEmit_r - This method is called by target-independent code
129 /// to request that an instruction with the given type and opcode
131 virtual unsigned FastEmit_(MVT VT,
135 /// FastEmit_r - This method is called by target-independent code
136 /// to request that an instruction with the given type, opcode, and
137 /// register operand be emitted.
139 virtual unsigned FastEmit_r(MVT VT,
141 unsigned Opcode, unsigned Op0);
143 /// FastEmit_rr - This method is called by target-independent code
144 /// to request that an instruction with the given type, opcode, and
145 /// register operands be emitted.
147 virtual unsigned FastEmit_rr(MVT VT,
150 unsigned Op0, unsigned Op1);
152 /// FastEmit_ri - This method is called by target-independent code
153 /// to request that an instruction with the given type, opcode, and
154 /// register and immediate operands be emitted.
156 virtual unsigned FastEmit_ri(MVT VT,
159 unsigned Op0, uint64_t Imm);
161 /// FastEmit_rf - This method is called by target-independent code
162 /// to request that an instruction with the given type, opcode, and
163 /// register and floating-point immediate operands be emitted.
165 virtual unsigned FastEmit_rf(MVT VT,
168 unsigned Op0, const ConstantFP *FPImm);
170 /// FastEmit_rri - This method is called by target-independent code
171 /// to request that an instruction with the given type, opcode, and
172 /// register and immediate operands be emitted.
174 virtual unsigned FastEmit_rri(MVT VT,
177 unsigned Op0, unsigned Op1, uint64_t Imm);
179 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
180 /// to emit an instruction with an immediate operand using FastEmit_ri.
181 /// If that fails, it materializes the immediate into a register and try
182 /// FastEmit_rr instead.
183 unsigned FastEmit_ri_(MVT VT,
185 unsigned Op0, uint64_t Imm,
188 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
189 /// to emit an instruction with an immediate operand using FastEmit_rf.
190 /// If that fails, it materializes the immediate into a register and try
191 /// FastEmit_rr instead.
192 unsigned FastEmit_rf_(MVT VT,
194 unsigned Op0, const ConstantFP *FPImm,
197 /// FastEmit_i - This method is called by target-independent code
198 /// to request that an instruction with the given type, opcode, and
199 /// immediate operand be emitted.
200 virtual unsigned FastEmit_i(MVT VT,
205 /// FastEmit_f - This method is called by target-independent code
206 /// to request that an instruction with the given type, opcode, and
207 /// floating-point immediate operand be emitted.
208 virtual unsigned FastEmit_f(MVT VT,
211 const ConstantFP *FPImm);
213 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
214 /// result register in the given register class.
216 unsigned FastEmitInst_(unsigned MachineInstOpcode,
217 const TargetRegisterClass *RC);
219 /// FastEmitInst_r - Emit a MachineInstr with one register operand
220 /// and a result register in the given register class.
222 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
223 const TargetRegisterClass *RC,
226 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
227 /// and a result register in the given register class.
229 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
230 const TargetRegisterClass *RC,
231 unsigned Op0, unsigned Op1);
233 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
234 /// and a result register in the given register class.
236 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
237 const TargetRegisterClass *RC,
238 unsigned Op0, uint64_t Imm);
240 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
241 /// and a result register in the given register class.
243 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
244 const TargetRegisterClass *RC,
245 unsigned Op0, const ConstantFP *FPImm);
247 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
248 /// an immediate, and a result register in the given register class.
250 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
251 const TargetRegisterClass *RC,
252 unsigned Op0, unsigned Op1, uint64_t Imm);
254 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
255 /// operand, and a result register in the given register class.
256 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
257 const TargetRegisterClass *RC,
260 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
261 /// from a specified index of a superregister to a specified type.
262 unsigned FastEmitInst_extractsubreg(MVT RetVT,
263 unsigned Op0, uint32_t Idx);
265 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
266 /// with all but the least significant bit set to zero.
267 unsigned FastEmitZExtFromI1(MVT VT,
270 /// FastEmitBranch - Emit an unconditional branch to the given block,
271 /// unless it is the immediate (fall-through) successor, and update
273 void FastEmitBranch(MachineBasicBlock *MBB);
275 unsigned UpdateValueMap(const Value* I, unsigned Reg);
277 unsigned createResultReg(const TargetRegisterClass *RC);
279 /// TargetMaterializeConstant - Emit a constant in a register using
280 /// target-specific logic, such as constant pool loads.
281 virtual unsigned TargetMaterializeConstant(const Constant* C) {
285 /// TargetMaterializeAlloca - Emit an alloca address in a register using
286 /// target-specific logic.
287 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
292 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
294 bool SelectFNeg(const User *I);
296 bool SelectGetElementPtr(const User *I);
298 bool SelectCall(const User *I);
300 bool SelectBitCast(const User *I);
302 bool SelectCast(const User *I, unsigned Opcode);