1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class MachineBasicBlock;
26 class MachineConstantPool;
27 class MachineFunction;
28 class MachineFrameInfo;
29 class MachineRegisterInfo;
31 class TargetInstrInfo;
34 class TargetRegisterClass;
36 /// FastISel - This is a fast-path instruction selection class that
37 /// generates poor code and doesn't support illegal types or non-trivial
38 /// lowering, but runs quickly.
41 MachineBasicBlock *MBB;
42 DenseMap<const Value *, unsigned> LocalValueMap;
43 DenseMap<const Value *, unsigned> &ValueMap;
44 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
45 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
47 MachineRegisterInfo &MRI;
48 MachineFrameInfo &MFI;
49 MachineConstantPool &MCP;
50 const TargetMachine &TM;
52 const TargetInstrInfo &TII;
53 const TargetLowering &TLI;
56 /// setCurrentBlock - Set the current block, to which generated
57 /// machine instructions will be appended.
59 void setCurrentBlock(MachineBasicBlock *mbb) {
63 /// SelectInstruction - Do "fast" instruction selection for the given
64 /// LLVM IR instruction, and append generated machine instructions to
65 /// the current block. Return true if selection was successful.
67 bool SelectInstruction(Instruction *I);
69 /// SelectInstruction - Do "fast" instruction selection for the given
70 /// LLVM IR operator (Instruction or ConstantExpr), and append
71 /// generated machine instructions to the current block. Return true
72 /// if selection was successful.
74 bool SelectOperator(User *I, unsigned Opcode);
76 /// TargetSelectInstruction - This method is called by target-independent
77 /// code when the normal FastISel process fails to select an instruction.
78 /// This gives targets a chance to emit code for anything that doesn't
79 /// fit into FastISel's framework. It returns true if it was successful.
82 TargetSelectInstruction(Instruction *I) = 0;
84 /// getRegForValue - Create a virtual register and arrange for it to
85 /// be assigned the value for the given LLVM value.
86 unsigned getRegForValue(Value *V);
88 /// lookUpRegForValue - Look up the value to see if its value is already
89 /// cached in a register. It may be defined by instructions across blocks or
91 unsigned lookUpRegForValue(Value *V);
96 FastISel(MachineFunction &mf,
97 DenseMap<const Value *, unsigned> &vm,
98 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
99 DenseMap<const AllocaInst *, int> &am);
101 /// FastEmit_r - This method is called by target-independent code
102 /// to request that an instruction with the given type and opcode
104 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
105 MVT::SimpleValueType RetVT,
106 ISD::NodeType Opcode);
108 /// FastEmit_r - This method is called by target-independent code
109 /// to request that an instruction with the given type, opcode, and
110 /// register operand be emitted.
112 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
113 MVT::SimpleValueType RetVT,
114 ISD::NodeType Opcode, unsigned Op0);
116 /// FastEmit_rr - This method is called by target-independent code
117 /// to request that an instruction with the given type, opcode, and
118 /// register operands be emitted.
120 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
121 MVT::SimpleValueType RetVT,
122 ISD::NodeType Opcode,
123 unsigned Op0, unsigned Op1);
125 /// FastEmit_ri - This method is called by target-independent code
126 /// to request that an instruction with the given type, opcode, and
127 /// register and immediate operands be emitted.
129 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
130 MVT::SimpleValueType RetVT,
131 ISD::NodeType Opcode,
132 unsigned Op0, uint64_t Imm);
134 /// FastEmit_rf - This method is called by target-independent code
135 /// to request that an instruction with the given type, opcode, and
136 /// register and floating-point immediate operands be emitted.
138 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
139 MVT::SimpleValueType RetVT,
140 ISD::NodeType Opcode,
141 unsigned Op0, ConstantFP *FPImm);
143 /// FastEmit_rri - This method is called by target-independent code
144 /// to request that an instruction with the given type, opcode, and
145 /// register and immediate operands be emitted.
147 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
148 MVT::SimpleValueType RetVT,
149 ISD::NodeType Opcode,
150 unsigned Op0, unsigned Op1, uint64_t Imm);
152 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
153 /// to emit an instruction with an immediate operand using FastEmit_ri.
154 /// If that fails, it materializes the immediate into a register and try
155 /// FastEmit_rr instead.
156 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
157 ISD::NodeType Opcode,
158 unsigned Op0, uint64_t Imm,
159 MVT::SimpleValueType ImmType);
161 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
162 /// to emit an instruction with an immediate operand using FastEmit_rf.
163 /// If that fails, it materializes the immediate into a register and try
164 /// FastEmit_rr instead.
165 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
166 ISD::NodeType Opcode,
167 unsigned Op0, ConstantFP *FPImm,
168 MVT::SimpleValueType ImmType);
170 /// FastEmit_i - This method is called by target-independent code
171 /// to request that an instruction with the given type, opcode, and
172 /// immediate operand be emitted.
173 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
174 MVT::SimpleValueType RetVT,
175 ISD::NodeType Opcode,
178 /// FastEmit_f - This method is called by target-independent code
179 /// to request that an instruction with the given type, opcode, and
180 /// floating-point immediate operand be emitted.
181 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
182 MVT::SimpleValueType RetVT,
183 ISD::NodeType Opcode,
186 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
187 /// result register in the given register class.
189 unsigned FastEmitInst_(unsigned MachineInstOpcode,
190 const TargetRegisterClass *RC);
192 /// FastEmitInst_r - Emit a MachineInstr with one register operand
193 /// and a result register in the given register class.
195 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
196 const TargetRegisterClass *RC,
199 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
200 /// and a result register in the given register class.
202 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
203 const TargetRegisterClass *RC,
204 unsigned Op0, unsigned Op1);
206 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
207 /// and a result register in the given register class.
209 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
210 const TargetRegisterClass *RC,
211 unsigned Op0, uint64_t Imm);
213 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
214 /// and a result register in the given register class.
216 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
217 const TargetRegisterClass *RC,
218 unsigned Op0, ConstantFP *FPImm);
220 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
221 /// an immediate, and a result register in the given register class.
223 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC,
225 unsigned Op0, unsigned Op1, uint64_t Imm);
227 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
228 /// operand, and a result register in the given register class.
229 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
230 const TargetRegisterClass *RC,
233 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
234 /// from a specified index of a superregister.
235 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
237 void UpdateValueMap(Value* I, unsigned Reg);
239 unsigned createResultReg(const TargetRegisterClass *RC);
241 /// TargetMaterializeConstant - Emit a constant in a register using
242 /// target-specific logic, such as constant pool loads.
243 virtual unsigned TargetMaterializeConstant(Constant* C) {
247 /// TargetMaterializeAlloca - Emit an alloca address in a register using
248 /// target-specific logic.
249 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
254 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
256 bool SelectGetElementPtr(User *I);
258 bool SelectBitCast(User *I);
260 bool SelectCast(User *I, ISD::NodeType Opcode);