1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineBasicBlock;
29 class MachineConstantPool;
30 class MachineFunction;
32 class MachineFrameInfo;
33 class MachineRegisterInfo;
35 class TargetInstrInfo;
38 class TargetRegisterClass;
40 /// FastISel - This is a fast-path instruction selection class that
41 /// generates poor code and doesn't support illegal types or non-trivial
42 /// lowering, but runs quickly.
45 MachineBasicBlock *MBB;
46 DenseMap<const Value *, unsigned> LocalValueMap;
47 DenseMap<const Value *, unsigned> &ValueMap;
48 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
49 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
52 SmallSet<const Instruction *, 8> &CatchInfoLost;
55 MachineRegisterInfo &MRI;
56 MachineFrameInfo &MFI;
57 MachineConstantPool &MCP;
59 const TargetMachine &TM;
61 const TargetInstrInfo &TII;
62 const TargetLowering &TLI;
66 /// startNewBlock - Set the current block to which generated machine
67 /// instructions will be appended, and clear the local CSE map.
69 void startNewBlock(MachineBasicBlock *mbb) {
71 LocalValueMap.clear();
74 /// setCurrentBlock - Set the current block to which generated machine
75 /// instructions will be appended.
77 void setCurrentBlock(MachineBasicBlock *mbb) {
81 /// getCurDebugLoc() - Return current debug location information.
82 DebugLoc getCurDebugLoc() const { return DL; }
84 /// SelectInstruction - Do "fast" instruction selection for the given
85 /// LLVM IR instruction, and append generated machine instructions to
86 /// the current block. Return true if selection was successful.
88 bool SelectInstruction(const Instruction *I);
90 /// SelectOperator - Do "fast" instruction selection for the given
91 /// LLVM IR operator (Instruction or ConstantExpr), and append
92 /// generated machine instructions to the current block. Return true
93 /// if selection was successful.
95 bool SelectOperator(const User *I, unsigned Opcode);
97 /// getRegForValue - Create a virtual register and arrange for it to
98 /// be assigned the value for the given LLVM value.
99 unsigned getRegForValue(const Value *V);
101 /// lookUpRegForValue - Look up the value to see if its value is already
102 /// cached in a register. It may be defined by instructions across blocks or
104 unsigned lookUpRegForValue(const Value *V);
106 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
107 /// takes care of truncating or sign-extending the given getelementptr
109 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
114 FastISel(MachineFunction &mf,
115 DenseMap<const Value *, unsigned> &vm,
116 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
117 DenseMap<const AllocaInst *, int> &am,
118 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
120 , SmallSet<const Instruction *, 8> &cil
124 /// TargetSelectInstruction - This method is called by target-independent
125 /// code when the normal FastISel process fails to select an instruction.
126 /// This gives targets a chance to emit code for anything that doesn't
127 /// fit into FastISel's framework. It returns true if it was successful.
130 TargetSelectInstruction(const Instruction *I) = 0;
132 /// FastEmit_r - This method is called by target-independent code
133 /// to request that an instruction with the given type and opcode
135 virtual unsigned FastEmit_(MVT VT,
139 /// FastEmit_r - This method is called by target-independent code
140 /// to request that an instruction with the given type, opcode, and
141 /// register operand be emitted.
143 virtual unsigned FastEmit_r(MVT VT,
146 unsigned Op0, bool Op0IsKill);
148 /// FastEmit_rr - This method is called by target-independent code
149 /// to request that an instruction with the given type, opcode, and
150 /// register operands be emitted.
152 virtual unsigned FastEmit_rr(MVT VT,
155 unsigned Op0, bool Op0IsKill,
156 unsigned Op1, bool Op1IsKill);
158 /// FastEmit_ri - This method is called by target-independent code
159 /// to request that an instruction with the given type, opcode, and
160 /// register and immediate operands be emitted.
162 virtual unsigned FastEmit_ri(MVT VT,
165 unsigned Op0, bool Op0IsKill,
168 /// FastEmit_rf - This method is called by target-independent code
169 /// to request that an instruction with the given type, opcode, and
170 /// register and floating-point immediate operands be emitted.
172 virtual unsigned FastEmit_rf(MVT VT,
175 unsigned Op0, bool Op0IsKill,
176 const ConstantFP *FPImm);
178 /// FastEmit_rri - This method is called by target-independent code
179 /// to request that an instruction with the given type, opcode, and
180 /// register and immediate operands be emitted.
182 virtual unsigned FastEmit_rri(MVT VT,
185 unsigned Op0, bool Op0IsKill,
186 unsigned Op1, bool Op1IsKill,
189 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
190 /// to emit an instruction with an immediate operand using FastEmit_ri.
191 /// If that fails, it materializes the immediate into a register and try
192 /// FastEmit_rr instead.
193 unsigned FastEmit_ri_(MVT VT,
195 unsigned Op0, bool Op0IsKill,
196 uint64_t Imm, MVT ImmType);
198 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
199 /// to emit an instruction with an immediate operand using FastEmit_rf.
200 /// If that fails, it materializes the immediate into a register and try
201 /// FastEmit_rr instead.
202 unsigned FastEmit_rf_(MVT VT,
204 unsigned Op0, bool Op0IsKill,
205 const ConstantFP *FPImm, MVT ImmType);
207 /// FastEmit_i - This method is called by target-independent code
208 /// to request that an instruction with the given type, opcode, and
209 /// immediate operand be emitted.
210 virtual unsigned FastEmit_i(MVT VT,
215 /// FastEmit_f - This method is called by target-independent code
216 /// to request that an instruction with the given type, opcode, and
217 /// floating-point immediate operand be emitted.
218 virtual unsigned FastEmit_f(MVT VT,
221 const ConstantFP *FPImm);
223 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
224 /// result register in the given register class.
226 unsigned FastEmitInst_(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC);
229 /// FastEmitInst_r - Emit a MachineInstr with one register operand
230 /// and a result register in the given register class.
232 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
233 const TargetRegisterClass *RC,
234 unsigned Op0, bool Op0IsKill);
236 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
237 /// and a result register in the given register class.
239 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
240 const TargetRegisterClass *RC,
241 unsigned Op0, bool Op0IsKill,
242 unsigned Op1, bool Op1IsKill);
244 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
245 /// and a result register in the given register class.
247 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
248 const TargetRegisterClass *RC,
249 unsigned Op0, bool Op0IsKill,
252 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
253 /// and a result register in the given register class.
255 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
256 const TargetRegisterClass *RC,
257 unsigned Op0, bool Op0IsKill,
258 const ConstantFP *FPImm);
260 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
261 /// an immediate, and a result register in the given register class.
263 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
264 const TargetRegisterClass *RC,
265 unsigned Op0, bool Op0IsKill,
266 unsigned Op1, bool Op1IsKill,
269 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
270 /// operand, and a result register in the given register class.
271 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
272 const TargetRegisterClass *RC,
275 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
276 /// from a specified index of a superregister to a specified type.
277 unsigned FastEmitInst_extractsubreg(MVT RetVT,
278 unsigned Op0, bool Op0IsKill,
281 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
282 /// with all but the least significant bit set to zero.
283 unsigned FastEmitZExtFromI1(MVT VT,
284 unsigned Op0, bool Op0IsKill);
286 /// FastEmitBranch - Emit an unconditional branch to the given block,
287 /// unless it is the immediate (fall-through) successor, and update
289 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
291 unsigned UpdateValueMap(const Value* I, unsigned Reg);
293 unsigned createResultReg(const TargetRegisterClass *RC);
295 /// TargetMaterializeConstant - Emit a constant in a register using
296 /// target-specific logic, such as constant pool loads.
297 virtual unsigned TargetMaterializeConstant(const Constant* C) {
301 /// TargetMaterializeAlloca - Emit an alloca address in a register using
302 /// target-specific logic.
303 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
308 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
310 bool SelectFNeg(const User *I);
312 bool SelectGetElementPtr(const User *I);
314 bool SelectCall(const User *I);
316 bool SelectBitCast(const User *I);
318 bool SelectCast(const User *I, unsigned Opcode);
320 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
321 /// Emit code to ensure constants are copied into registers when needed.
322 /// Remember the virtual registers that need to be added to the Machine PHI
323 /// nodes as input. We cannot just directly add them, because expansion
324 /// might result in multiple MBB's for one BB. As such, the start of the
325 /// BB might correspond to a different MBB than the end.
326 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
328 /// materializeRegForValue - Helper for getRegForVale. This function is
329 /// called when the value isn't already available in a register and must
330 /// be materialized with new instructions.
331 unsigned materializeRegForValue(const Value *V, MVT VT);
333 /// hasTrivialKill - Test whether the given value has exactly one use.
334 bool hasTrivialKill(const Value *V) const;