1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class MachineBasicBlock;
25 class MachineFunction;
26 class MachineRegisterInfo;
28 class TargetInstrInfo;
31 class TargetRegisterClass;
33 /// FastISel - This is a fast-path instruction selection class that
34 /// generates poor code and doesn't support illegal types or non-trivial
35 /// lowering, but runs quickly.
38 MachineBasicBlock *MBB;
39 DenseMap<const Value *, unsigned> LocalValueMap;
40 DenseMap<const Value *, unsigned> &ValueMap;
41 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
43 MachineRegisterInfo &MRI;
44 const TargetMachine &TM;
46 const TargetInstrInfo &TII;
47 const TargetLowering &TLI;
50 /// setCurrentBlock - Set the current block, to which generated
51 /// machine instructions will be appended.
53 void setCurrentBlock(MachineBasicBlock *mbb) {
57 /// SelectInstruction - Do "fast" instruction selection for the given
58 /// LLVM IR instruction, and append generated machine instructions to
59 /// the current block. Return true if selection was successful.
61 bool SelectInstruction(Instruction *I);
63 /// TargetSelectInstruction - This method is called by target-independent
64 /// code when the normal FastISel process fails to select an instruction.
65 /// This gives targets a chance to emit code for anything that doesn't
66 /// fit into FastISel's framework. It returns true if it was successful.
69 TargetSelectInstruction(Instruction *I) = 0;
71 /// getRegForValue - Create a virtual register and arrange for it to
72 /// be assigned the value for the given LLVM value.
73 unsigned getRegForValue(Value *V);
78 FastISel(MachineFunction &mf,
79 DenseMap<const Value *, unsigned> &vm,
80 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm);
82 /// FastEmit_r - This method is called by target-independent code
83 /// to request that an instruction with the given type and opcode
85 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
86 MVT::SimpleValueType RetVT,
87 ISD::NodeType Opcode);
89 /// FastEmit_r - This method is called by target-independent code
90 /// to request that an instruction with the given type, opcode, and
91 /// register operand be emitted.
93 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
94 MVT::SimpleValueType RetVT,
95 ISD::NodeType Opcode, unsigned Op0);
97 /// FastEmit_rr - This method is called by target-independent code
98 /// to request that an instruction with the given type, opcode, and
99 /// register operands be emitted.
101 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
102 MVT::SimpleValueType RetVT,
103 ISD::NodeType Opcode,
104 unsigned Op0, unsigned Op1);
106 /// FastEmit_ri - This method is called by target-independent code
107 /// to request that an instruction with the given type, opcode, and
108 /// register and immediate operands be emitted.
110 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
111 MVT::SimpleValueType RetVT,
112 ISD::NodeType Opcode,
113 unsigned Op0, uint64_t Imm);
115 /// FastEmit_rf - This method is called by target-independent code
116 /// to request that an instruction with the given type, opcode, and
117 /// register and floating-point immediate operands be emitted.
119 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
120 MVT::SimpleValueType RetVT,
121 ISD::NodeType Opcode,
122 unsigned Op0, ConstantFP *FPImm);
124 /// FastEmit_rri - This method is called by target-independent code
125 /// to request that an instruction with the given type, opcode, and
126 /// register and immediate operands be emitted.
128 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
129 MVT::SimpleValueType RetVT,
130 ISD::NodeType Opcode,
131 unsigned Op0, unsigned Op1, uint64_t Imm);
133 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
134 /// to emit an instruction with an immediate operand using FastEmit_ri.
135 /// If that fails, it materializes the immediate into a register and try
136 /// FastEmit_rr instead.
137 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
138 ISD::NodeType Opcode,
139 unsigned Op0, uint64_t Imm,
140 MVT::SimpleValueType ImmType);
142 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
143 /// to emit an instruction with an immediate operand using FastEmit_rf.
144 /// If that fails, it materializes the immediate into a register and try
145 /// FastEmit_rr instead.
146 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
147 ISD::NodeType Opcode,
148 unsigned Op0, ConstantFP *FPImm,
149 MVT::SimpleValueType ImmType);
151 /// FastEmit_i - This method is called by target-independent code
152 /// to request that an instruction with the given type, opcode, and
153 /// immediate operand be emitted.
154 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
155 MVT::SimpleValueType RetVT,
156 ISD::NodeType Opcode,
159 /// FastEmit_f - This method is called by target-independent code
160 /// to request that an instruction with the given type, opcode, and
161 /// floating-point immediate operand be emitted.
162 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
163 MVT::SimpleValueType RetVT,
164 ISD::NodeType Opcode,
167 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
168 /// result register in the given register class.
170 unsigned FastEmitInst_(unsigned MachineInstOpcode,
171 const TargetRegisterClass *RC);
173 /// FastEmitInst_r - Emit a MachineInstr with one register operand
174 /// and a result register in the given register class.
176 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
177 const TargetRegisterClass *RC,
180 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
181 /// and a result register in the given register class.
183 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
184 const TargetRegisterClass *RC,
185 unsigned Op0, unsigned Op1);
187 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
188 /// and a result register in the given register class.
190 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
191 const TargetRegisterClass *RC,
192 unsigned Op0, uint64_t Imm);
194 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
195 /// and a result register in the given register class.
197 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
198 const TargetRegisterClass *RC,
199 unsigned Op0, ConstantFP *FPImm);
201 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
202 /// an immediate, and a result register in the given register class.
204 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
205 const TargetRegisterClass *RC,
206 unsigned Op0, unsigned Op1, uint64_t Imm);
208 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
209 /// operand, and a result register in the given register class.
210 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
211 const TargetRegisterClass *RC,
214 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
215 /// from a specified index of a superregister.
216 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
218 void UpdateValueMap(Instruction* I, unsigned Reg);
220 unsigned createResultReg(const TargetRegisterClass *RC);
223 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode);
225 bool SelectGetElementPtr(Instruction *I);
227 bool SelectBitCast(Instruction *I);
229 bool SelectCast(Instruction *I, ISD::NodeType Opcode);