1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineFrameInfo;
31 class MachineModuleInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
39 /// FastISel - This is a fast-path instruction selection class that
40 /// generates poor code and doesn't support illegal types or non-trivial
41 /// lowering, but runs quickly.
44 MachineBasicBlock *MBB;
45 DenseMap<const Value *, unsigned> LocalValueMap;
46 DenseMap<const Value *, unsigned> &ValueMap;
47 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 SmallSet<Instruction*, 8> &CatchInfoLost;
53 MachineModuleInfo *MMI;
54 MachineRegisterInfo &MRI;
55 MachineFrameInfo &MFI;
56 MachineConstantPool &MCP;
57 const TargetMachine &TM;
59 const TargetInstrInfo &TII;
60 const TargetLowering &TLI;
63 /// startNewBlock - Set the current block, to which generated
64 /// machine instructions will be appended, and clear the local
67 void startNewBlock(MachineBasicBlock *mbb) {
69 LocalValueMap.clear();
72 /// setCurrentBlock - Set the current block, to which generated
73 /// machine instructions will be appended.
75 void setCurrentBlock(MachineBasicBlock *mbb) {
79 /// SelectInstruction - Do "fast" instruction selection for the given
80 /// LLVM IR instruction, and append generated machine instructions to
81 /// the current block. Return true if selection was successful.
83 bool SelectInstruction(Instruction *I);
85 /// SelectInstruction - Do "fast" instruction selection for the given
86 /// LLVM IR operator (Instruction or ConstantExpr), and append
87 /// generated machine instructions to the current block. Return true
88 /// if selection was successful.
90 bool SelectOperator(User *I, unsigned Opcode);
92 /// TargetSelectInstruction - This method is called by target-independent
93 /// code when the normal FastISel process fails to select an instruction.
94 /// This gives targets a chance to emit code for anything that doesn't
95 /// fit into FastISel's framework. It returns true if it was successful.
98 TargetSelectInstruction(Instruction *I) = 0;
100 /// getRegForValue - Create a virtual register and arrange for it to
101 /// be assigned the value for the given LLVM value.
102 unsigned getRegForValue(Value *V);
104 /// lookUpRegForValue - Look up the value to see if its value is already
105 /// cached in a register. It may be defined by instructions across blocks or
107 unsigned lookUpRegForValue(Value *V);
112 FastISel(MachineFunction &mf,
113 MachineModuleInfo *mmi,
114 DenseMap<const Value *, unsigned> &vm,
115 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
116 DenseMap<const AllocaInst *, int> &am
118 , SmallSet<Instruction*, 8> &cil
122 /// FastEmit_r - This method is called by target-independent code
123 /// to request that an instruction with the given type and opcode
125 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
126 MVT::SimpleValueType RetVT,
127 ISD::NodeType Opcode);
129 /// FastEmit_r - This method is called by target-independent code
130 /// to request that an instruction with the given type, opcode, and
131 /// register operand be emitted.
133 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
134 MVT::SimpleValueType RetVT,
135 ISD::NodeType Opcode, unsigned Op0);
137 /// FastEmit_rr - This method is called by target-independent code
138 /// to request that an instruction with the given type, opcode, and
139 /// register operands be emitted.
141 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
142 MVT::SimpleValueType RetVT,
143 ISD::NodeType Opcode,
144 unsigned Op0, unsigned Op1);
146 /// FastEmit_ri - This method is called by target-independent code
147 /// to request that an instruction with the given type, opcode, and
148 /// register and immediate operands be emitted.
150 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
151 MVT::SimpleValueType RetVT,
152 ISD::NodeType Opcode,
153 unsigned Op0, uint64_t Imm);
155 /// FastEmit_rf - This method is called by target-independent code
156 /// to request that an instruction with the given type, opcode, and
157 /// register and floating-point immediate operands be emitted.
159 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
160 MVT::SimpleValueType RetVT,
161 ISD::NodeType Opcode,
162 unsigned Op0, ConstantFP *FPImm);
164 /// FastEmit_rri - This method is called by target-independent code
165 /// to request that an instruction with the given type, opcode, and
166 /// register and immediate operands be emitted.
168 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
169 MVT::SimpleValueType RetVT,
170 ISD::NodeType Opcode,
171 unsigned Op0, unsigned Op1, uint64_t Imm);
173 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
174 /// to emit an instruction with an immediate operand using FastEmit_ri.
175 /// If that fails, it materializes the immediate into a register and try
176 /// FastEmit_rr instead.
177 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
178 ISD::NodeType Opcode,
179 unsigned Op0, uint64_t Imm,
180 MVT::SimpleValueType ImmType);
182 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
183 /// to emit an instruction with an immediate operand using FastEmit_rf.
184 /// If that fails, it materializes the immediate into a register and try
185 /// FastEmit_rr instead.
186 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
187 ISD::NodeType Opcode,
188 unsigned Op0, ConstantFP *FPImm,
189 MVT::SimpleValueType ImmType);
191 /// FastEmit_i - This method is called by target-independent code
192 /// to request that an instruction with the given type, opcode, and
193 /// immediate operand be emitted.
194 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
195 MVT::SimpleValueType RetVT,
196 ISD::NodeType Opcode,
199 /// FastEmit_f - This method is called by target-independent code
200 /// to request that an instruction with the given type, opcode, and
201 /// floating-point immediate operand be emitted.
202 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
203 MVT::SimpleValueType RetVT,
204 ISD::NodeType Opcode,
207 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
208 /// result register in the given register class.
210 unsigned FastEmitInst_(unsigned MachineInstOpcode,
211 const TargetRegisterClass *RC);
213 /// FastEmitInst_r - Emit a MachineInstr with one register operand
214 /// and a result register in the given register class.
216 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
217 const TargetRegisterClass *RC,
220 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
221 /// and a result register in the given register class.
223 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC,
225 unsigned Op0, unsigned Op1);
227 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
228 /// and a result register in the given register class.
230 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
231 const TargetRegisterClass *RC,
232 unsigned Op0, uint64_t Imm);
234 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
235 /// and a result register in the given register class.
237 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
238 const TargetRegisterClass *RC,
239 unsigned Op0, ConstantFP *FPImm);
241 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
242 /// an immediate, and a result register in the given register class.
244 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
245 const TargetRegisterClass *RC,
246 unsigned Op0, unsigned Op1, uint64_t Imm);
248 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
249 /// operand, and a result register in the given register class.
250 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
251 const TargetRegisterClass *RC,
254 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
255 /// from a specified index of a superregister.
256 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
258 /// FastEmitBranch - Emit an unconditional branch to the given block,
259 /// unless it is the immediate (fall-through) successor, and update
261 void FastEmitBranch(MachineBasicBlock *MBB);
263 void UpdateValueMap(Value* I, unsigned Reg);
265 unsigned createResultReg(const TargetRegisterClass *RC);
267 /// TargetMaterializeConstant - Emit a constant in a register using
268 /// target-specific logic, such as constant pool loads.
269 virtual unsigned TargetMaterializeConstant(Constant* C) {
273 /// TargetMaterializeAlloca - Emit an alloca address in a register using
274 /// target-specific logic.
275 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
280 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
282 bool SelectGetElementPtr(User *I);
284 bool SelectCall(User *I);
286 bool SelectBitCast(User *I);
288 bool SelectCast(User *I, ISD::NodeType Opcode);