1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class MachineBasicBlock;
25 class MachineFunction;
26 class MachineRegisterInfo;
28 class TargetInstrInfo;
31 class TargetRegisterClass;
33 /// FastISel - This is a fast-path instruction selection class that
34 /// generates poor code and doesn't support illegal types or non-trivial
35 /// lowering, but runs quickly.
38 MachineBasicBlock *MBB;
40 MachineRegisterInfo &MRI;
41 const TargetMachine &TM;
43 const TargetInstrInfo &TII;
44 const TargetLowering &TLI;
47 /// SelectInstructions - Do "fast" instruction selection over the
48 /// LLVM IR instructions in the range [Begin, N) where N is either
49 /// End or the first unsupported instruction. Return N.
50 /// ValueMap is filled in with a mapping of LLVM IR Values to
51 /// virtual register numbers. MBB is a block to which to append
52 /// the generated MachineInstrs.
54 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
55 DenseMap<const Value *, unsigned> &ValueMap,
56 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
57 MachineBasicBlock *MBB);
59 /// TargetSelectInstruction - This method is called by target-independent
60 /// code when the normal FastISel process fails to select an instruction.
61 /// This gives targets a chance to emit code for anything that doesn't
62 /// fit into FastISel's framework. It returns true if it was successful.
65 TargetSelectInstruction(Instruction *I,
66 DenseMap<const Value *, unsigned> &ValueMap,
67 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
68 MachineBasicBlock *MBB) = 0;
73 explicit FastISel(MachineFunction &mf);
75 /// FastEmit_r - This method is called by target-independent code
76 /// to request that an instruction with the given type and opcode
78 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
79 MVT::SimpleValueType RetVT,
80 ISD::NodeType Opcode);
82 /// FastEmit_r - This method is called by target-independent code
83 /// to request that an instruction with the given type, opcode, and
84 /// register operand be emitted.
86 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
87 MVT::SimpleValueType RetVT,
88 ISD::NodeType Opcode, unsigned Op0);
90 /// FastEmit_rr - This method is called by target-independent code
91 /// to request that an instruction with the given type, opcode, and
92 /// register operands be emitted.
94 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
95 MVT::SimpleValueType RetVT,
97 unsigned Op0, unsigned Op1);
99 /// FastEmit_ri - This method is called by target-independent code
100 /// to request that an instruction with the given type, opcode, and
101 /// register and immediate operands be emitted.
103 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
104 MVT::SimpleValueType RetVT,
105 ISD::NodeType Opcode,
106 unsigned Op0, uint64_t Imm);
108 /// FastEmit_rf - This method is called by target-independent code
109 /// to request that an instruction with the given type, opcode, and
110 /// register and floating-point immediate operands be emitted.
112 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
113 MVT::SimpleValueType RetVT,
114 ISD::NodeType Opcode,
115 unsigned Op0, ConstantFP *FPImm);
117 /// FastEmit_rri - This method is called by target-independent code
118 /// to request that an instruction with the given type, opcode, and
119 /// register and immediate operands be emitted.
121 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
122 MVT::SimpleValueType RetVT,
123 ISD::NodeType Opcode,
124 unsigned Op0, unsigned Op1, uint64_t Imm);
126 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
127 /// to emit an instruction with an immediate operand using FastEmit_ri.
128 /// If that fails, it materializes the immediate into a register and try
129 /// FastEmit_rr instead.
130 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
131 ISD::NodeType Opcode,
132 unsigned Op0, uint64_t Imm,
133 MVT::SimpleValueType ImmType);
135 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
136 /// to emit an instruction with an immediate operand using FastEmit_rf.
137 /// If that fails, it materializes the immediate into a register and try
138 /// FastEmit_rr instead.
139 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
140 ISD::NodeType Opcode,
141 unsigned Op0, ConstantFP *FPImm,
142 MVT::SimpleValueType ImmType);
144 /// FastEmit_i - This method is called by target-independent code
145 /// to request that an instruction with the given type, opcode, and
146 /// immediate operand be emitted.
147 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
148 MVT::SimpleValueType RetVT,
149 ISD::NodeType Opcode,
152 /// FastEmit_f - This method is called by target-independent code
153 /// to request that an instruction with the given type, opcode, and
154 /// floating-point immediate operand be emitted.
155 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
156 MVT::SimpleValueType RetVT,
157 ISD::NodeType Opcode,
160 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
161 /// result register in the given register class.
163 unsigned FastEmitInst_(unsigned MachineInstOpcode,
164 const TargetRegisterClass *RC);
166 /// FastEmitInst_r - Emit a MachineInstr with one register operand
167 /// and a result register in the given register class.
169 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
170 const TargetRegisterClass *RC,
173 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
174 /// and a result register in the given register class.
176 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
177 const TargetRegisterClass *RC,
178 unsigned Op0, unsigned Op1);
180 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
181 /// and a result register in the given register class.
183 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
184 const TargetRegisterClass *RC,
185 unsigned Op0, uint64_t Imm);
187 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
188 /// and a result register in the given register class.
190 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
191 const TargetRegisterClass *RC,
192 unsigned Op0, ConstantFP *FPImm);
194 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
195 /// an immediate, and a result register in the given register class.
197 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
198 const TargetRegisterClass *RC,
199 unsigned Op0, unsigned Op1, uint64_t Imm);
201 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
202 /// operand, and a result register in the given register class.
203 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
204 const TargetRegisterClass *RC,
207 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
208 /// from a specified index of a superregister.
209 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
211 unsigned getRegForValue(Value *V,
212 DenseMap<const Value*, unsigned> &ValueMap);
214 void UpdateValueMap(Instruction* I, unsigned Reg,
215 DenseMap<const Value*, unsigned> &ValueMap);
217 unsigned createResultReg(const TargetRegisterClass *RC);
220 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
221 DenseMap<const Value*, unsigned> &ValueMap);
223 bool SelectGetElementPtr(Instruction *I,
224 DenseMap<const Value*, unsigned> &ValueMap);
226 bool SelectBitCast(Instruction *I,
227 DenseMap<const Value*, unsigned> &ValueMap);
229 bool SelectCast(Instruction *I, ISD::NodeType Opcode,
230 DenseMap<const Value*, unsigned> &ValueMap);