1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class MachineBasicBlock;
26 class MachineConstantPool;
27 class MachineFunction;
28 class MachineFrameInfo;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetInstrInfo;
35 class TargetRegisterClass;
37 /// FastISel - This is a fast-path instruction selection class that
38 /// generates poor code and doesn't support illegal types or non-trivial
39 /// lowering, but runs quickly.
42 MachineBasicBlock *MBB;
43 DenseMap<const Value *, unsigned> LocalValueMap;
44 DenseMap<const Value *, unsigned> &ValueMap;
45 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
46 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
48 MachineModuleInfo *MMI;
49 MachineRegisterInfo &MRI;
50 MachineFrameInfo &MFI;
51 MachineConstantPool &MCP;
52 const TargetMachine &TM;
54 const TargetInstrInfo &TII;
55 const TargetLowering &TLI;
58 /// setCurrentBlock - Set the current block, to which generated
59 /// machine instructions will be appended.
61 void setCurrentBlock(MachineBasicBlock *mbb) {
63 LocalValueMap.clear();
66 /// SelectInstruction - Do "fast" instruction selection for the given
67 /// LLVM IR instruction, and append generated machine instructions to
68 /// the current block. Return true if selection was successful.
70 bool SelectInstruction(Instruction *I);
72 /// SelectInstruction - Do "fast" instruction selection for the given
73 /// LLVM IR operator (Instruction or ConstantExpr), and append
74 /// generated machine instructions to the current block. Return true
75 /// if selection was successful.
77 bool SelectOperator(User *I, unsigned Opcode);
79 /// TargetSelectInstruction - This method is called by target-independent
80 /// code when the normal FastISel process fails to select an instruction.
81 /// This gives targets a chance to emit code for anything that doesn't
82 /// fit into FastISel's framework. It returns true if it was successful.
85 TargetSelectInstruction(Instruction *I) = 0;
87 /// getRegForValue - Create a virtual register and arrange for it to
88 /// be assigned the value for the given LLVM value.
89 unsigned getRegForValue(Value *V);
91 /// lookUpRegForValue - Look up the value to see if its value is already
92 /// cached in a register. It may be defined by instructions across blocks or
94 unsigned lookUpRegForValue(Value *V);
99 FastISel(MachineFunction &mf,
100 MachineModuleInfo *mmi,
101 DenseMap<const Value *, unsigned> &vm,
102 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
103 DenseMap<const AllocaInst *, int> &am);
105 /// FastEmit_r - This method is called by target-independent code
106 /// to request that an instruction with the given type and opcode
108 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
109 MVT::SimpleValueType RetVT,
110 ISD::NodeType Opcode);
112 /// FastEmit_r - This method is called by target-independent code
113 /// to request that an instruction with the given type, opcode, and
114 /// register operand be emitted.
116 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
117 MVT::SimpleValueType RetVT,
118 ISD::NodeType Opcode, unsigned Op0);
120 /// FastEmit_rr - This method is called by target-independent code
121 /// to request that an instruction with the given type, opcode, and
122 /// register operands be emitted.
124 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
125 MVT::SimpleValueType RetVT,
126 ISD::NodeType Opcode,
127 unsigned Op0, unsigned Op1);
129 /// FastEmit_ri - This method is called by target-independent code
130 /// to request that an instruction with the given type, opcode, and
131 /// register and immediate operands be emitted.
133 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
134 MVT::SimpleValueType RetVT,
135 ISD::NodeType Opcode,
136 unsigned Op0, uint64_t Imm);
138 /// FastEmit_rf - This method is called by target-independent code
139 /// to request that an instruction with the given type, opcode, and
140 /// register and floating-point immediate operands be emitted.
142 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
143 MVT::SimpleValueType RetVT,
144 ISD::NodeType Opcode,
145 unsigned Op0, ConstantFP *FPImm);
147 /// FastEmit_rri - This method is called by target-independent code
148 /// to request that an instruction with the given type, opcode, and
149 /// register and immediate operands be emitted.
151 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
152 MVT::SimpleValueType RetVT,
153 ISD::NodeType Opcode,
154 unsigned Op0, unsigned Op1, uint64_t Imm);
156 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
157 /// to emit an instruction with an immediate operand using FastEmit_ri.
158 /// If that fails, it materializes the immediate into a register and try
159 /// FastEmit_rr instead.
160 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
161 ISD::NodeType Opcode,
162 unsigned Op0, uint64_t Imm,
163 MVT::SimpleValueType ImmType);
165 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
166 /// to emit an instruction with an immediate operand using FastEmit_rf.
167 /// If that fails, it materializes the immediate into a register and try
168 /// FastEmit_rr instead.
169 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
170 ISD::NodeType Opcode,
171 unsigned Op0, ConstantFP *FPImm,
172 MVT::SimpleValueType ImmType);
174 /// FastEmit_i - This method is called by target-independent code
175 /// to request that an instruction with the given type, opcode, and
176 /// immediate operand be emitted.
177 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
178 MVT::SimpleValueType RetVT,
179 ISD::NodeType Opcode,
182 /// FastEmit_f - This method is called by target-independent code
183 /// to request that an instruction with the given type, opcode, and
184 /// floating-point immediate operand be emitted.
185 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
186 MVT::SimpleValueType RetVT,
187 ISD::NodeType Opcode,
190 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
191 /// result register in the given register class.
193 unsigned FastEmitInst_(unsigned MachineInstOpcode,
194 const TargetRegisterClass *RC);
196 /// FastEmitInst_r - Emit a MachineInstr with one register operand
197 /// and a result register in the given register class.
199 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
200 const TargetRegisterClass *RC,
203 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
204 /// and a result register in the given register class.
206 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
207 const TargetRegisterClass *RC,
208 unsigned Op0, unsigned Op1);
210 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
211 /// and a result register in the given register class.
213 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
214 const TargetRegisterClass *RC,
215 unsigned Op0, uint64_t Imm);
217 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
218 /// and a result register in the given register class.
220 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
221 const TargetRegisterClass *RC,
222 unsigned Op0, ConstantFP *FPImm);
224 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
225 /// an immediate, and a result register in the given register class.
227 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC,
229 unsigned Op0, unsigned Op1, uint64_t Imm);
231 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
232 /// operand, and a result register in the given register class.
233 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
234 const TargetRegisterClass *RC,
237 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
238 /// from a specified index of a superregister.
239 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
241 void UpdateValueMap(Value* I, unsigned Reg);
243 unsigned createResultReg(const TargetRegisterClass *RC);
245 /// TargetMaterializeConstant - Emit a constant in a register using
246 /// target-specific logic, such as constant pool loads.
247 virtual unsigned TargetMaterializeConstant(Constant* C) {
251 /// TargetMaterializeAlloca - Emit an alloca address in a register using
252 /// target-specific logic.
253 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
258 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
260 bool SelectGetElementPtr(User *I);
262 bool SelectCall(User *I);
264 bool SelectBitCast(User *I);
266 bool SelectCast(User *I, ISD::NodeType Opcode);