1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class MachineBasicBlock;
25 class MachineConstantPool;
26 class MachineFunction;
27 class MachineRegisterInfo;
29 class TargetInstrInfo;
32 class TargetRegisterClass;
34 /// FastISel - This is a fast-path instruction selection class that
35 /// generates poor code and doesn't support illegal types or non-trivial
36 /// lowering, but runs quickly.
39 MachineBasicBlock *MBB;
40 DenseMap<const Value *, unsigned> LocalValueMap;
41 DenseMap<const Value *, unsigned> &ValueMap;
42 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
44 MachineRegisterInfo &MRI;
45 const TargetMachine &TM;
47 const TargetInstrInfo &TII;
48 const TargetLowering &TLI;
51 /// setCurrentBlock - Set the current block, to which generated
52 /// machine instructions will be appended.
54 void setCurrentBlock(MachineBasicBlock *mbb) {
58 /// SelectInstruction - Do "fast" instruction selection for the given
59 /// LLVM IR instruction, and append generated machine instructions to
60 /// the current block. Return true if selection was successful.
62 bool SelectInstruction(Instruction *I);
64 /// TargetSelectInstruction - This method is called by target-independent
65 /// code when the normal FastISel process fails to select an instruction.
66 /// This gives targets a chance to emit code for anything that doesn't
67 /// fit into FastISel's framework. It returns true if it was successful.
70 TargetSelectInstruction(Instruction *I) = 0;
72 /// getRegForValue - Create a virtual register and arrange for it to
73 /// be assigned the value for the given LLVM value.
74 unsigned getRegForValue(Value *V);
79 FastISel(MachineFunction &mf,
80 DenseMap<const Value *, unsigned> &vm,
81 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm);
83 /// FastEmit_r - This method is called by target-independent code
84 /// to request that an instruction with the given type and opcode
86 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
87 MVT::SimpleValueType RetVT,
88 ISD::NodeType Opcode);
90 /// FastEmit_r - This method is called by target-independent code
91 /// to request that an instruction with the given type, opcode, and
92 /// register operand be emitted.
94 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
95 MVT::SimpleValueType RetVT,
96 ISD::NodeType Opcode, unsigned Op0);
98 /// FastEmit_rr - This method is called by target-independent code
99 /// to request that an instruction with the given type, opcode, and
100 /// register operands be emitted.
102 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
103 MVT::SimpleValueType RetVT,
104 ISD::NodeType Opcode,
105 unsigned Op0, unsigned Op1);
107 /// FastEmit_ri - This method is called by target-independent code
108 /// to request that an instruction with the given type, opcode, and
109 /// register and immediate operands be emitted.
111 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
112 MVT::SimpleValueType RetVT,
113 ISD::NodeType Opcode,
114 unsigned Op0, uint64_t Imm);
116 /// FastEmit_rf - This method is called by target-independent code
117 /// to request that an instruction with the given type, opcode, and
118 /// register and floating-point immediate operands be emitted.
120 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
121 MVT::SimpleValueType RetVT,
122 ISD::NodeType Opcode,
123 unsigned Op0, ConstantFP *FPImm);
125 /// FastEmit_rri - This method is called by target-independent code
126 /// to request that an instruction with the given type, opcode, and
127 /// register and immediate operands be emitted.
129 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
130 MVT::SimpleValueType RetVT,
131 ISD::NodeType Opcode,
132 unsigned Op0, unsigned Op1, uint64_t Imm);
134 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
135 /// to emit an instruction with an immediate operand using FastEmit_ri.
136 /// If that fails, it materializes the immediate into a register and try
137 /// FastEmit_rr instead.
138 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
139 ISD::NodeType Opcode,
140 unsigned Op0, uint64_t Imm,
141 MVT::SimpleValueType ImmType);
143 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
144 /// to emit an instruction with an immediate operand using FastEmit_rf.
145 /// If that fails, it materializes the immediate into a register and try
146 /// FastEmit_rr instead.
147 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
148 ISD::NodeType Opcode,
149 unsigned Op0, ConstantFP *FPImm,
150 MVT::SimpleValueType ImmType);
152 /// FastEmit_i - This method is called by target-independent code
153 /// to request that an instruction with the given type, opcode, and
154 /// immediate operand be emitted.
155 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
156 MVT::SimpleValueType RetVT,
157 ISD::NodeType Opcode,
160 /// FastEmit_f - This method is called by target-independent code
161 /// to request that an instruction with the given type, opcode, and
162 /// floating-point immediate operand be emitted.
163 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
164 MVT::SimpleValueType RetVT,
165 ISD::NodeType Opcode,
168 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
169 /// result register in the given register class.
171 unsigned FastEmitInst_(unsigned MachineInstOpcode,
172 const TargetRegisterClass *RC);
174 /// FastEmitInst_r - Emit a MachineInstr with one register operand
175 /// and a result register in the given register class.
177 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
178 const TargetRegisterClass *RC,
181 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
182 /// and a result register in the given register class.
184 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
185 const TargetRegisterClass *RC,
186 unsigned Op0, unsigned Op1);
188 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
189 /// and a result register in the given register class.
191 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
192 const TargetRegisterClass *RC,
193 unsigned Op0, uint64_t Imm);
195 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
196 /// and a result register in the given register class.
198 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
199 const TargetRegisterClass *RC,
200 unsigned Op0, ConstantFP *FPImm);
202 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
203 /// an immediate, and a result register in the given register class.
205 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC,
207 unsigned Op0, unsigned Op1, uint64_t Imm);
209 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
210 /// operand, and a result register in the given register class.
211 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
212 const TargetRegisterClass *RC,
215 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
216 /// from a specified index of a superregister.
217 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
219 void UpdateValueMap(Value* I, unsigned Reg);
221 unsigned createResultReg(const TargetRegisterClass *RC);
223 virtual unsigned TargetSelectConstantPoolLoad(Constant* C,
224 MachineConstantPool* MCP) {
229 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode);
231 bool SelectGetElementPtr(Instruction *I);
233 bool SelectBitCast(Instruction *I);
235 bool SelectCast(Instruction *I, ISD::NodeType Opcode);