1 //===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file defines the FastISel class.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_FASTISEL_H
16 #define LLVM_CODEGEN_FASTISEL_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/IntrinsicInst.h"
32 class FunctionLoweringInfo;
36 class MachineConstantPool;
37 class MachineFrameInfo;
38 class MachineFunction;
40 class MachineRegisterInfo;
41 class TargetInstrInfo;
42 class TargetLibraryInfo;
45 class TargetRegisterClass;
46 class TargetRegisterInfo;
50 /// This is a fast-path instruction selection class that generates poor code and
51 /// doesn't support illegal types or non-trivial lowering, but runs quickly.
68 : Val(nullptr), Ty(nullptr), isSExt(false), isZExt(false), isInReg(false),
69 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
70 isReturned(false), Alignment(0) { }
72 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
74 typedef std::vector<ArgListEntry> ArgListTy;
76 struct CallLoweringInfo {
82 bool DoesNotReturn : 1;
83 bool IsReturnValueUsed : 1;
85 // IsTailCall should be modified by implementations of
86 // FastLowerCall that perform tail call conversions.
89 unsigned NumFixedArgs;
90 CallingConv::ID CallConv;
94 ImmutableCallSite *CS;
97 unsigned NumResultRegs;
99 SmallVector<Value *, 16> OutVals;
100 SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
101 SmallVector<unsigned, 16> OutRegs;
102 SmallVector<ISD::InputArg, 4> Ins;
103 SmallVector<unsigned, 4> InRegs;
106 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
107 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
108 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
109 Callee(nullptr), SymName(nullptr), CS(nullptr), Call(nullptr),
110 ResultReg(0), NumResultRegs(0)
113 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
114 const Value *Target, ArgListTy &&ArgsList,
115 ImmutableCallSite &Call) {
119 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
120 DoesNotReturn = Call.doesNotReturn();
121 IsVarArg = FuncTy->isVarArg();
122 IsReturnValueUsed = !Call.getInstruction()->use_empty();
123 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
124 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
126 CallConv = Call.getCallingConv();
127 NumFixedArgs = FuncTy->getNumParams();
128 Args = std::move(ArgsList);
135 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
136 const char *Target, ArgListTy &&ArgsList,
137 ImmutableCallSite &Call,
138 unsigned FixedArgs = ~0U) {
140 Callee = Call.getCalledValue();
143 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
144 DoesNotReturn = Call.doesNotReturn();
145 IsVarArg = FuncTy->isVarArg();
146 IsReturnValueUsed = !Call.getInstruction()->use_empty();
147 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
148 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
150 CallConv = Call.getCallingConv();
151 NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
152 Args = std::move(ArgsList);
159 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
160 const Value *Target, ArgListTy &&ArgsList,
161 unsigned FixedArgs = ~0U) {
165 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
166 Args = std::move(ArgsList);
170 CallLoweringInfo &setTailCall(bool Value = true) {
175 ArgListTy &getArgs() {
192 DenseMap<const Value *, unsigned> LocalValueMap;
193 FunctionLoweringInfo &FuncInfo;
195 MachineRegisterInfo &MRI;
196 MachineFrameInfo &MFI;
197 MachineConstantPool &MCP;
199 const TargetMachine &TM;
200 const DataLayout &DL;
201 const TargetInstrInfo &TII;
202 const TargetLowering &TLI;
203 const TargetRegisterInfo &TRI;
204 const TargetLibraryInfo *LibInfo;
206 /// The position of the last instruction for materializing constants for use
207 /// in the current block. It resets to EmitStartPt when it makes sense (for
208 /// example, it's usually profitable to avoid function calls between the
209 /// definition and the use)
210 MachineInstr *LastLocalValue;
212 /// The top most instruction in the current block that is allowed for emitting
213 /// local variables. LastLocalValue resets to EmitStartPt when it makes sense
214 /// (for example, on function calls)
215 MachineInstr *EmitStartPt;
218 /// Return the position of the last instruction emitted for materializing
219 /// constants for use in the current block.
220 MachineInstr *getLastLocalValue() { return LastLocalValue; }
222 /// Update the position of the last instruction emitted for materializing
223 /// constants for use in the current block.
224 void setLastLocalValue(MachineInstr *I) {
229 /// Set the current block to which generated machine instructions will be
230 /// appended, and clear the local CSE map.
231 void startNewBlock();
233 /// Return current debug location information.
234 DebugLoc getCurDebugLoc() const { return DbgLoc; }
236 /// Do "fast" instruction selection for function arguments and append machine
237 /// instructions to the current block. Return true if it is successful.
238 bool LowerArguments();
240 /// Do "fast" instruction selection for the given LLVM IR instruction, and
241 /// append generated machine instructions to the current block. Return true if
242 /// selection was successful.
243 bool SelectInstruction(const Instruction *I);
245 /// Do "fast" instruction selection for the given LLVM IR operator
246 /// (Instruction or ConstantExpr), and append generated machine instructions
247 /// to the current block. Return true if selection was successful.
248 bool SelectOperator(const User *I, unsigned Opcode);
250 /// Create a virtual register and arrange for it to be assigned the value for
251 /// the given LLVM value.
252 unsigned getRegForValue(const Value *V);
254 /// Look up the value to see if its value is already cached in a register. It
255 /// may be defined by instructions across blocks or defined locally.
256 unsigned lookUpRegForValue(const Value *V);
258 /// This is a wrapper around getRegForValue that also takes care of truncating
259 /// or sign-extending the given getelementptr index value.
260 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
262 /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
263 /// that we could have a sequence where multiple LLVM IR instructions are
264 /// folded into the same machineinstr. For example we could have:
266 /// A: x = load i32 *P
267 /// B: y = icmp A, 42
270 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
271 /// (and any other folded instructions) because it is between A and C.
273 /// If we succeed folding, return true.
274 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
276 /// \brief The specified machine instr operand is a vreg, and that vreg is
277 /// being provided by the specified load instruction. If possible, try to
278 /// fold the load as an operand to the instruction, returning true if
281 /// This method should be implemented by targets.
282 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
283 const LoadInst * /*LI*/) {
287 /// Reset InsertPt to prepare for inserting instructions into the current
289 void recomputeInsertPt();
291 /// Remove all dead instructions between the I and E.
292 void removeDeadCode(MachineBasicBlock::iterator I,
293 MachineBasicBlock::iterator E);
296 MachineBasicBlock::iterator InsertPt;
300 /// Prepare InsertPt to begin inserting instructions into the local value area
301 /// and return the old insert position.
302 SavePoint enterLocalValueArea();
304 /// Reset InsertPt to the given old insert position.
305 void leaveLocalValueArea(SavePoint Old);
310 explicit FastISel(FunctionLoweringInfo &funcInfo,
311 const TargetLibraryInfo *libInfo);
313 /// This method is called by target-independent code when the normal FastISel
314 /// process fails to select an instruction. This gives targets a chance to
315 /// emit code for anything that doesn't fit into FastISel's framework. It
316 /// returns true if it was successful.
317 virtual bool TargetSelectInstruction(const Instruction *I) = 0;
319 /// This method is called by target-independent code to do target specific
320 /// argument lowering. It returns true if it was successful.
321 virtual bool FastLowerArguments();
323 /// \brief This method is called by target-independent code to do target
324 /// specific call lowering. It returns true if it was successful.
325 virtual bool FastLowerCall(CallLoweringInfo &CLI);
327 /// \brief This method is called by target-independent code to do target
328 /// specific intrinsic lowering. It returns true if it was successful.
329 virtual bool FastLowerIntrinsicCall(const IntrinsicInst *II);
331 /// This method is called by target-independent code to request that an
332 /// instruction with the given type and opcode be emitted.
333 virtual unsigned FastEmit_(MVT VT,
337 /// This method is called by target-independent code to request that an
338 /// instruction with the given type, opcode, and register operand be emitted.
339 virtual unsigned FastEmit_r(MVT VT,
342 unsigned Op0, bool Op0IsKill);
344 /// This method is called by target-independent code to request that an
345 /// instruction with the given type, opcode, and register operands be emitted.
346 virtual unsigned FastEmit_rr(MVT VT,
349 unsigned Op0, bool Op0IsKill,
350 unsigned Op1, bool Op1IsKill);
352 /// This method is called by target-independent code to request that an
353 /// instruction with the given type, opcode, and register and immediate
354 /// operands be emitted.
355 virtual unsigned FastEmit_ri(MVT VT,
358 unsigned Op0, bool Op0IsKill,
361 /// This method is called by target-independent code to request that an
362 /// instruction with the given type, opcode, and register and floating-point
363 /// immediate operands be emitted.
364 virtual unsigned FastEmit_rf(MVT VT,
367 unsigned Op0, bool Op0IsKill,
368 const ConstantFP *FPImm);
370 /// This method is called by target-independent code to request that an
371 /// instruction with the given type, opcode, and register and immediate
372 /// operands be emitted.
373 virtual unsigned FastEmit_rri(MVT VT,
376 unsigned Op0, bool Op0IsKill,
377 unsigned Op1, bool Op1IsKill,
380 /// \brief This method is a wrapper of FastEmit_ri.
382 /// It first tries to emit an instruction with an immediate operand using
383 /// FastEmit_ri. If that fails, it materializes the immediate into a register
384 /// and try FastEmit_rr instead.
385 unsigned FastEmit_ri_(MVT VT,
387 unsigned Op0, bool Op0IsKill,
388 uint64_t Imm, MVT ImmType);
390 /// This method is called by target-independent code to request that an
391 /// instruction with the given type, opcode, and immediate operand be emitted.
392 virtual unsigned FastEmit_i(MVT VT,
397 /// This method is called by target-independent code to request that an
398 /// instruction with the given type, opcode, and floating-point immediate
399 /// operand be emitted.
400 virtual unsigned FastEmit_f(MVT VT,
403 const ConstantFP *FPImm);
405 /// Emit a MachineInstr with no operands and a result register in the given
407 unsigned FastEmitInst_(unsigned MachineInstOpcode,
408 const TargetRegisterClass *RC);
410 /// Emit a MachineInstr with one register operand and a result register in the
411 /// given register class.
412 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
413 const TargetRegisterClass *RC,
414 unsigned Op0, bool Op0IsKill);
416 /// Emit a MachineInstr with two register operands and a result register in
417 /// the given register class.
418 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
419 const TargetRegisterClass *RC,
420 unsigned Op0, bool Op0IsKill,
421 unsigned Op1, bool Op1IsKill);
423 /// Emit a MachineInstr with three register operands and a result register in
424 /// the given register class.
425 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
426 const TargetRegisterClass *RC,
427 unsigned Op0, bool Op0IsKill,
428 unsigned Op1, bool Op1IsKill,
429 unsigned Op2, bool Op2IsKill);
431 /// Emit a MachineInstr with a register operand, an immediate, and a result
432 /// register in the given register class.
433 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
434 const TargetRegisterClass *RC,
435 unsigned Op0, bool Op0IsKill,
438 /// Emit a MachineInstr with one register operand and two immediate operands.
439 unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
440 const TargetRegisterClass *RC,
441 unsigned Op0, bool Op0IsKill,
442 uint64_t Imm1, uint64_t Imm2);
444 /// Emit a MachineInstr with two register operands and a result register in
445 /// the given register class.
446 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
447 const TargetRegisterClass *RC,
448 unsigned Op0, bool Op0IsKill,
449 const ConstantFP *FPImm);
451 /// Emit a MachineInstr with two register operands, an immediate, and a result
452 /// register in the given register class.
453 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
454 const TargetRegisterClass *RC,
455 unsigned Op0, bool Op0IsKill,
456 unsigned Op1, bool Op1IsKill,
459 /// Emit a MachineInstr with two register operands, two immediates operands,
460 /// and a result register in the given register class.
461 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
462 const TargetRegisterClass *RC,
463 unsigned Op0, bool Op0IsKill,
464 unsigned Op1, bool Op1IsKill,
465 uint64_t Imm1, uint64_t Imm2);
467 /// Emit a MachineInstr with a single immediate operand, and a result register
468 /// in the given register class.
469 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
470 const TargetRegisterClass *RC,
473 /// Emit a MachineInstr with a two immediate operands.
474 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
475 const TargetRegisterClass *RC,
476 uint64_t Imm1, uint64_t Imm2);
478 /// Emit a MachineInstr for an extract_subreg from a specified index of a
479 /// superregister to a specified type.
480 unsigned FastEmitInst_extractsubreg(MVT RetVT,
481 unsigned Op0, bool Op0IsKill,
484 /// Emit MachineInstrs to compute the value of Op with all but the least
485 /// significant bit set to zero.
486 unsigned FastEmitZExtFromI1(MVT VT,
487 unsigned Op0, bool Op0IsKill);
489 /// Emit an unconditional branch to the given block, unless it is the
490 /// immediate (fall-through) successor, and update the CFG.
491 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
493 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
495 unsigned createResultReg(const TargetRegisterClass *RC);
497 /// Try to constrain Op so that it is usable by argument OpNum of the provided
498 /// MCInstrDesc. If this fails, create a new virtual register in the correct
499 /// class and COPY the value there.
500 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
503 /// Emit a constant in a register using target-specific logic, such as
504 /// constant pool loads.
505 virtual unsigned TargetMaterializeConstant(const Constant* C) {
509 /// Emit an alloca address in a register using target-specific logic.
510 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
514 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
518 /// \brief Check if \c Add is an add that can be safely folded into \c GEP.
520 /// \c Add can be folded into \c GEP if:
521 /// - \c Add is an add,
522 /// - \c Add's size matches \c GEP's,
523 /// - \c Add is in the same basic block as \c GEP, and
524 /// - \c Add has a constant operand.
525 bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
527 /// Test whether the given value has exactly one use.
528 bool hasTrivialKill(const Value *V) const;
530 /// \brief Create a machine mem operand from the given instruction.
531 MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
533 bool LowerCallTo(const CallInst *CI, const char *SymName, unsigned NumArgs);
534 bool LowerCallTo(CallLoweringInfo &CLI);
536 bool isCommutativeIntrinsic(IntrinsicInst const *II) {
537 switch (II->getIntrinsicID()) {
538 case Intrinsic::sadd_with_overflow:
539 case Intrinsic::uadd_with_overflow:
540 case Intrinsic::smul_with_overflow:
541 case Intrinsic::umul_with_overflow:
549 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
551 bool SelectFNeg(const User *I);
553 bool SelectGetElementPtr(const User *I);
555 bool SelectStackmap(const CallInst *I);
556 bool SelectPatchpoint(const CallInst *I);
557 bool LowerCall(const CallInst *I);
558 bool SelectCall(const User *Call);
559 bool SelectIntrinsicCall(const IntrinsicInst *II);
561 bool SelectBitCast(const User *I);
563 bool SelectCast(const User *I, unsigned Opcode);
565 bool SelectExtractValue(const User *I);
567 bool SelectInsertValue(const User *I);
569 /// \brief Handle PHI nodes in successor blocks.
571 /// Emit code to ensure constants are copied into registers when needed.
572 /// Remember the virtual registers that need to be added to the Machine PHI
573 /// nodes as input. We cannot just directly add them, because expansion might
574 /// result in multiple MBB's for one BB. As such, the start of the BB might
575 /// correspond to a different MBB than the end.
576 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
578 /// \brief Helper for materializeRegForValue to materialize a constant in a
579 /// target-independent way.
580 unsigned MaterializeConstant(const Value *V, MVT VT);
582 /// Helper for getRegForVale. This function is called when the value isn't
583 /// already available in a register and must be materialized with new
585 unsigned materializeRegForValue(const Value *V, MVT VT);
587 /// Clears LocalValueMap and moves the area for the new local variables to the
588 /// beginning of the block. It helps to avoid spilling cached variables across
589 /// heavy instructions like calls.
590 void flushLocalValueMap();
592 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
593 const CallInst *CI, unsigned StartIdx);
594 bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
595 const Value *Callee, bool ForceRetVoidTy,
596 CallLoweringInfo &CLI);