1 //===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file defines the FastISel class.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_FASTISEL_H
16 #define LLVM_CODEGEN_FASTISEL_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/IntrinsicInst.h"
27 /// \brief This is a fast-path instruction selection class that generates poor
28 /// code and doesn't support illegal types or non-trivial lowering, but runs
46 : Val(nullptr), Ty(nullptr), IsSExt(false), IsZExt(false),
47 IsInReg(false), IsSRet(false), IsNest(false), IsByVal(false),
48 IsInAlloca(false), IsReturned(false), Alignment(0) {}
50 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
51 /// and called function attributes.
52 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
54 typedef std::vector<ArgListEntry> ArgListTy;
56 struct CallLoweringInfo {
62 bool DoesNotReturn : 1;
63 bool IsReturnValueUsed : 1;
65 // \brief IsTailCall Should be modified by implementations of FastLowerCall
66 // that perform tail call conversions.
69 unsigned NumFixedArgs;
70 CallingConv::ID CallConv;
74 ImmutableCallSite *CS;
77 unsigned NumResultRegs;
79 SmallVector<Value *, 16> OutVals;
80 SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
81 SmallVector<unsigned, 16> OutRegs;
82 SmallVector<ISD::InputArg, 4> Ins;
83 SmallVector<unsigned, 4> InRegs;
86 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
87 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
88 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
89 Callee(nullptr), SymName(nullptr), CS(nullptr), Call(nullptr),
90 ResultReg(0), NumResultRegs(0) {}
92 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
93 const Value *Target, ArgListTy &&ArgsList,
94 ImmutableCallSite &Call) {
98 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
99 DoesNotReturn = Call.doesNotReturn();
100 IsVarArg = FuncTy->isVarArg();
101 IsReturnValueUsed = !Call.getInstruction()->use_empty();
102 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
103 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
105 CallConv = Call.getCallingConv();
106 NumFixedArgs = FuncTy->getNumParams();
107 Args = std::move(ArgsList);
114 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
115 const char *Target, ArgListTy &&ArgsList,
116 ImmutableCallSite &Call,
117 unsigned FixedArgs = ~0U) {
119 Callee = Call.getCalledValue();
122 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
123 DoesNotReturn = Call.doesNotReturn();
124 IsVarArg = FuncTy->isVarArg();
125 IsReturnValueUsed = !Call.getInstruction()->use_empty();
126 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
127 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
129 CallConv = Call.getCallingConv();
130 NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
131 Args = std::move(ArgsList);
138 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
139 const Value *Target, ArgListTy &&ArgsList,
140 unsigned FixedArgs = ~0U) {
144 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
145 Args = std::move(ArgsList);
149 CallLoweringInfo &setTailCall(bool Value = true) {
154 ArgListTy &getArgs() { return Args; }
169 DenseMap<const Value *, unsigned> LocalValueMap;
170 FunctionLoweringInfo &FuncInfo;
172 MachineRegisterInfo &MRI;
173 MachineFrameInfo &MFI;
174 MachineConstantPool &MCP;
176 const TargetMachine &TM;
177 const DataLayout &DL;
178 const TargetInstrInfo &TII;
179 const TargetLowering &TLI;
180 const TargetRegisterInfo &TRI;
181 const TargetLibraryInfo *LibInfo;
182 bool SkipTargetIndependentISel;
184 /// \brief The position of the last instruction for materializing constants
185 /// for use in the current block. It resets to EmitStartPt when it makes sense
186 /// (for example, it's usually profitable to avoid function calls between the
187 /// definition and the use)
188 MachineInstr *LastLocalValue;
190 /// \brief The top most instruction in the current block that is allowed for
191 /// emitting local variables. LastLocalValue resets to EmitStartPt when it
192 /// makes sense (for example, on function calls)
193 MachineInstr *EmitStartPt;
196 /// \brief Return the position of the last instruction emitted for
197 /// materializing constants for use in the current block.
198 MachineInstr *getLastLocalValue() { return LastLocalValue; }
200 /// \brief Update the position of the last instruction emitted for
201 /// materializing constants for use in the current block.
202 void setLastLocalValue(MachineInstr *I) {
207 /// \brief Set the current block to which generated machine instructions will
208 /// be appended, and clear the local CSE map.
209 void startNewBlock();
211 /// \brief Return current debug location information.
212 DebugLoc getCurDebugLoc() const { return DbgLoc; }
214 /// \brief Do "fast" instruction selection for function arguments and append
215 /// the machine instructions to the current block. Returns true when
217 bool LowerArguments();
219 /// \brief Do "fast" instruction selection for the given LLVM IR instruction
220 /// and append the generated machine instructions to the current block.
221 /// Returns true if selection was successful.
222 bool SelectInstruction(const Instruction *I);
224 /// \brief Do "fast" instruction selection for the given LLVM IR operator
225 /// (Instruction or ConstantExpr), and append generated machine instructions
226 /// to the current block. Return true if selection was successful.
227 bool selectOperator(const User *I, unsigned Opcode);
229 /// \brief Create a virtual register and arrange for it to be assigned the
230 /// value for the given LLVM value.
231 unsigned getRegForValue(const Value *V);
233 /// \brief Look up the value to see if its value is already cached in a
234 /// register. It may be defined by instructions across blocks or defined
236 unsigned lookUpRegForValue(const Value *V);
238 /// \brief This is a wrapper around getRegForValue that also takes care of
239 /// truncating or sign-extending the given getelementptr index value.
240 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
242 /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
243 /// that we could have a sequence where multiple LLVM IR instructions are
244 /// folded into the same machineinstr. For example we could have:
246 /// A: x = load i32 *P
247 /// B: y = icmp A, 42
250 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
251 /// (and any other folded instructions) because it is between A and C.
253 /// If we succeed folding, return true.
254 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
256 /// \brief The specified machine instr operand is a vreg, and that vreg is
257 /// being provided by the specified load instruction. If possible, try to
258 /// fold the load as an operand to the instruction, returning true if
261 /// This method should be implemented by targets.
262 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
263 const LoadInst * /*LI*/) {
267 /// \brief Reset InsertPt to prepare for inserting instructions into the
269 void recomputeInsertPt();
271 /// \brief Remove all dead instructions between the I and E.
272 void removeDeadCode(MachineBasicBlock::iterator I,
273 MachineBasicBlock::iterator E);
276 MachineBasicBlock::iterator InsertPt;
280 /// \brief Prepare InsertPt to begin inserting instructions into the local
281 /// value area and return the old insert position.
282 SavePoint enterLocalValueArea();
284 /// \brief Reset InsertPt to the given old insert position.
285 void leaveLocalValueArea(SavePoint Old);
290 explicit FastISel(FunctionLoweringInfo &FuncInfo,
291 const TargetLibraryInfo *LibInfo,
292 bool SkipTargetIndependentISel = false);
294 /// \brief This method is called by target-independent code when the normal
295 /// FastISel process fails to select an instruction. This gives targets a
296 /// chance to emit code for anything that doesn't fit into FastISel's
297 /// framework. It returns true if it was successful.
298 virtual bool TargetSelectInstruction(const Instruction *I) = 0;
300 /// \brief This method is called by target-independent code to do target-
301 /// specific argument lowering. It returns true if it was successful.
302 virtual bool FastLowerArguments();
304 /// \brief This method is called by target-independent code to do target-
305 /// specific call lowering. It returns true if it was successful.
306 virtual bool FastLowerCall(CallLoweringInfo &CLI);
308 /// \brief This method is called by target-independent code to do target-
309 /// specific intrinsic lowering. It returns true if it was successful.
310 virtual bool FastLowerIntrinsicCall(const IntrinsicInst *II);
312 /// \brief This method is called by target-independent code to request that an
313 /// instruction with the given type and opcode be emitted.
314 virtual unsigned FastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
316 /// \brief This method is called by target-independent code to request that an
317 /// instruction with the given type, opcode, and register operand be emitted.
318 virtual unsigned FastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
321 /// \brief This method is called by target-independent code to request that an
322 /// instruction with the given type, opcode, and register operands be emitted.
323 virtual unsigned FastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
324 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
326 /// \brief This method is called by target-independent code to request that an
327 /// instruction with the given type, opcode, and register and immediate
328 // operands be emitted.
329 virtual unsigned FastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
330 bool Op0IsKill, uint64_t Imm);
332 /// \brief This method is called by target-independent code to request that an
333 /// instruction with the given type, opcode, and register and floating-point
334 /// immediate operands be emitted.
335 virtual unsigned FastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
336 bool Op0IsKill, const ConstantFP *FPImm);
338 /// \brief This method is called by target-independent code to request that an
339 /// instruction with the given type, opcode, and register and immediate
340 /// operands be emitted.
341 virtual unsigned FastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode,
342 unsigned Op0, bool Op0IsKill, unsigned Op1,
343 bool Op1IsKill, uint64_t Imm);
345 /// \brief This method is a wrapper of FastEmit_ri.
347 /// It first tries to emit an instruction with an immediate operand using
348 /// FastEmit_ri. If that fails, it materializes the immediate into a register
349 /// and try FastEmit_rr instead.
350 unsigned FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
351 uint64_t Imm, MVT ImmType);
353 /// \brief This method is called by target-independent code to request that an
354 /// instruction with the given type, opcode, and immediate operand be emitted.
355 virtual unsigned FastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
357 /// \brief This method is called by target-independent code to request that an
358 /// instruction with the given type, opcode, and floating-point immediate
359 /// operand be emitted.
360 virtual unsigned FastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
361 const ConstantFP *FPImm);
363 /// \brief Emit a MachineInstr with no operands and a result register in the
364 /// given register class.
365 unsigned FastEmitInst_(unsigned MachineInstOpcode,
366 const TargetRegisterClass *RC);
368 /// \brief Emit a MachineInstr with one register operand and a result register
369 /// in the given register class.
370 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
371 const TargetRegisterClass *RC, unsigned Op0,
374 /// \brief Emit a MachineInstr with two register operands and a result
375 /// register in the given register class.
376 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
377 const TargetRegisterClass *RC, unsigned Op0,
378 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
380 /// \brief Emit a MachineInstr with three register operands and a result
381 /// register in the given register class.
382 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
383 const TargetRegisterClass *RC, unsigned Op0,
384 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
385 unsigned Op2, bool Op2IsKill);
387 /// \brief Emit a MachineInstr with a register operand, an immediate, and a
388 /// result register in the given register class.
389 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
390 const TargetRegisterClass *RC, unsigned Op0,
391 bool Op0IsKill, uint64_t Imm);
393 /// \brief Emit a MachineInstr with one register operand and two immediate
395 unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
396 const TargetRegisterClass *RC, unsigned Op0,
397 bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
399 /// \brief Emit a MachineInstr with two register operands and a result
400 /// register in the given register class.
401 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
402 const TargetRegisterClass *RC, unsigned Op0,
403 bool Op0IsKill, const ConstantFP *FPImm);
405 /// \brief Emit a MachineInstr with two register operands, an immediate, and a
406 /// result register in the given register class.
407 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
408 const TargetRegisterClass *RC, unsigned Op0,
409 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
412 /// \brief Emit a MachineInstr with two register operands, two immediates
413 /// operands, and a result register in the given register class.
414 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
415 const TargetRegisterClass *RC, unsigned Op0,
416 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
417 uint64_t Imm1, uint64_t Imm2);
419 /// \brief Emit a MachineInstr with a single immediate operand, and a result
420 /// register in the given register class.
421 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
422 const TargetRegisterClass *RC, uint64_t Imm);
424 /// \brief Emit a MachineInstr with a two immediate operands.
425 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
426 const TargetRegisterClass *RC, uint64_t Imm1,
429 /// \brief Emit a MachineInstr for an extract_subreg from a specified index of
430 /// a superregister to a specified type.
431 unsigned FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
434 /// \brief Emit MachineInstrs to compute the value of Op with all but the
435 /// least significant bit set to zero.
436 unsigned FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
438 /// \brief Emit an unconditional branch to the given block, unless it is the
439 /// immediate (fall-through) successor, and update the CFG.
440 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
442 /// \brief Update the value map to include the new mapping for this
443 /// instruction, or insert an extra copy to get the result in a previous
444 /// determined register.
446 /// NOTE: This is only necessary because we might select a block that uses a
447 /// value before we select the block that defines the value. It might be
448 /// possible to fix this by selecting blocks in reverse postorder.
449 void UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
451 unsigned createResultReg(const TargetRegisterClass *RC);
453 /// \brief Try to constrain Op so that it is usable by argument OpNum of the
454 /// provided MCInstrDesc. If this fails, create a new virtual register in the
455 /// correct class and COPY the value there.
456 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
459 /// \brief Emit a constant in a register using target-specific logic, such as
460 /// constant pool loads.
461 virtual unsigned TargetMaterializeConstant(const Constant *C) { return 0; }
463 /// \brief Emit an alloca address in a register using target-specific logic.
464 virtual unsigned TargetMaterializeAlloca(const AllocaInst *C) { return 0; }
466 /// \brief Emit the floating-point constant +0.0 in a register using target-
468 virtual unsigned TargetMaterializeFloatZero(const ConstantFP *CF) {
472 /// \brief Check if \c Add is an add that can be safely folded into \c GEP.
474 /// \c Add can be folded into \c GEP if:
475 /// - \c Add is an add,
476 /// - \c Add's size matches \c GEP's,
477 /// - \c Add is in the same basic block as \c GEP, and
478 /// - \c Add has a constant operand.
479 bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
481 /// \brief Test whether the given value has exactly one use.
482 bool hasTrivialKill(const Value *V);
484 /// \brief Create a machine mem operand from the given instruction.
485 MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
487 bool LowerCallTo(const CallInst *CI, const char *SymName, unsigned NumArgs);
488 bool lowerCallTo(CallLoweringInfo &CLI);
490 bool isCommutativeIntrinsic(IntrinsicInst const *II) {
491 switch (II->getIntrinsicID()) {
492 case Intrinsic::sadd_with_overflow:
493 case Intrinsic::uadd_with_overflow:
494 case Intrinsic::smul_with_overflow:
495 case Intrinsic::umul_with_overflow:
502 /// \brief Select and emit code for a binary operator instruction, which has
503 /// an opcode which directly corresponds to the given ISD opcode.
504 bool selectBinaryOp(const User *I, unsigned ISDOpcode);
505 bool selectFNeg(const User *I);
506 bool selectGetElementPtr(const User *I);
507 bool selectStackmap(const CallInst *I);
508 bool selectPatchpoint(const CallInst *I);
509 bool lowerCall(const CallInst *I);
510 bool selectCall(const User *Call);
511 bool selectIntrinsicCall(const IntrinsicInst *II);
512 bool selectBitCast(const User *I);
513 bool selectCast(const User *I, unsigned Opcode);
514 bool selectExtractValue(const User *I);
515 bool selectInsertValue(const User *I);
518 /// \brief Handle PHI nodes in successor blocks.
520 /// Emit code to ensure constants are copied into registers when needed.
521 /// Remember the virtual registers that need to be added to the Machine PHI
522 /// nodes as input. We cannot just directly add them, because expansion might
523 /// result in multiple MBB's for one BB. As such, the start of the BB might
524 /// correspond to a different MBB than the end.
525 bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
527 /// \brief Helper for materializeRegForValue to materialize a constant in a
528 /// target-independent way.
529 unsigned materializeConstant(const Value *V, MVT VT);
531 /// \brief Helper for getRegForVale. This function is called when the value
532 /// isn't already available in a register and must be materialized with new
534 unsigned materializeRegForValue(const Value *V, MVT VT);
536 /// \brief Clears LocalValueMap and moves the area for the new local variables
537 /// to the beginning of the block. It helps to avoid spilling cached variables
538 /// across heavy instructions like calls.
539 void flushLocalValueMap();
541 /// \brief Add a stackmap or patchpoint intrinsic call's live variable
542 /// operands to a stackmap or patchpoint machine instruction.
543 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
544 const CallInst *CI, unsigned StartIdx);
545 bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
546 const Value *Callee, bool ForceRetVoidTy,
547 CallLoweringInfo &CLI);
550 } // end namespace llvm