1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MachineRegisterInfo;
27 class TargetInstrInfo;
30 class TargetRegisterClass;
32 /// FastISel - This is a fast-path instruction selection class that
33 /// generates poor code and doesn't support illegal types or non-trivial
34 /// lowering, but runs quickly.
37 MachineBasicBlock *MBB;
39 MachineRegisterInfo &MRI;
40 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
46 /// SelectInstructions - Do "fast" instruction selection over the
47 /// LLVM IR instructions in the range [Begin, N) where N is either
48 /// End or the first unsupported instruction. Return N.
49 /// ValueMap is filled in with a mapping of LLVM IR Values to
50 /// virtual register numbers. MBB is a block to which to append
51 /// the generated MachineInstrs.
53 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
54 DenseMap<const Value*, unsigned> &ValueMap,
55 DenseMap<const BasicBlock*, MachineBasicBlock *> &MBBMap,
56 MachineBasicBlock *MBB);
61 explicit FastISel(MachineFunction &mf);
63 /// FastEmit_r - This method is called by target-independent code
64 /// to request that an instruction with the given type and opcode
66 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
67 ISD::NodeType Opcode);
69 /// FastEmit_r - This method is called by target-independent code
70 /// to request that an instruction with the given type, opcode, and
71 /// register operand be emitted.
73 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
74 ISD::NodeType Opcode, unsigned Op0);
76 /// FastEmit_rr - This method is called by target-independent code
77 /// to request that an instruction with the given type, opcode, and
78 /// register operands be emitted.
80 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
82 unsigned Op0, unsigned Op1);
84 /// FastEmit_ri - This method is called by target-independent code
85 /// to request that an instruction with the given type, opcode, and
86 /// register and immediate operands be emitted.
88 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
90 unsigned Op0, uint64_t Imm);
92 /// FastEmit_rri - This method is called by target-independent code
93 /// to request that an instruction with the given type, opcode, and
94 /// register and immediate operands be emitted.
96 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
98 unsigned Op0, unsigned Op1, uint64_t Imm);
100 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
101 /// to emit an instruction with an immediate operand using FastEmit_ri.
102 /// If that fails, it materializes the immediate into a register and try
103 /// FastEmit_rr instead.
104 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
105 ISD::NodeType Opcode,
106 unsigned Op0, uint64_t Imm,
107 MVT::SimpleValueType ImmType);
109 /// FastEmit_i - This method is called by target-independent code
110 /// to request that an instruction with the given type, opcode, and
111 /// immediate operand be emitted.
112 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
113 ISD::NodeType Opcode,
116 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
117 /// result register in the given register class.
119 unsigned FastEmitInst_(unsigned MachineInstOpcode,
120 const TargetRegisterClass *RC);
122 /// FastEmitInst_r - Emit a MachineInstr with one register operand
123 /// and a result register in the given register class.
125 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
126 const TargetRegisterClass *RC,
129 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
130 /// and a result register in the given register class.
132 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
133 const TargetRegisterClass *RC,
134 unsigned Op0, unsigned Op1);
136 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
137 /// and a result register in the given register class.
139 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
140 const TargetRegisterClass *RC,
141 unsigned Op0, uint64_t Imm);
143 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
144 /// an immediate, and a result register in the given register class.
146 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
147 const TargetRegisterClass *RC,
148 unsigned Op0, unsigned Op1, uint64_t Imm);
150 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
151 /// operand, and a result register in the given register class.
152 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
153 const TargetRegisterClass *RC,
157 unsigned createResultReg(const TargetRegisterClass *RC);
159 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
160 DenseMap<const Value*, unsigned> &ValueMap);
162 bool SelectGetElementPtr(Instruction *I,
163 DenseMap<const Value*, unsigned> &ValueMap);