1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MachineRegisterInfo;
27 class TargetInstrInfo;
29 class TargetRegisterClass;
31 /// FastISel - This is a fast-path instruction selection class that
32 /// generates poor code and doesn't support illegal types or non-trivial
33 /// lowering, but runs quickly.
35 MachineBasicBlock *MBB;
37 MachineRegisterInfo &MRI;
39 const TargetInstrInfo &TII;
43 /// SelectInstructions - Do "fast" instruction selection over the
44 /// LLVM IR instructions in the range [Begin, N) where N is either
45 /// End or the first unsupported instruction. Return N.
46 /// ValueMap is filled in with a mapping of LLVM IR Values to
47 /// virtual register numbers. MBB is a block to which to append
48 /// the enerated MachineInstrs.
50 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
51 DenseMap<const Value*, unsigned> &ValueMap,
52 MachineBasicBlock *MBB);
57 explicit FastISel(MachineFunction &mf);
59 /// FastEmit_r - This method is called by target-independent code
60 /// to request that an instruction with the given type and opcode
62 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
63 ISD::NodeType Opcode);
65 /// FastEmit_r - This method is called by target-independent code
66 /// to request that an instruction with the given type, opcode, and
67 /// register operand be emitted.
69 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
70 ISD::NodeType Opcode, unsigned Op0);
72 /// FastEmit_rr - This method is called by target-independent code
73 /// to request that an instruction with the given type, opcode, and
74 /// register operands be emitted.
76 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
78 unsigned Op0, unsigned Op1);
80 /// FastEmit_i - This method is called by target-independent code
81 /// to request that an instruction with the given type which materialize
82 /// the specified immediate value.
83 virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
85 /// FastEmit_ri - This method is called by target-independent code
86 /// to request that an instruction with the given type, opcode, and
87 /// register and immediate operands be emitted.
89 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
91 unsigned Op0, uint64_t Imm);
93 /// FastEmit_rri - This method is called by target-independent code
94 /// to request that an instruction with the given type, opcode, and
95 /// register and immediate operands be emitted.
97 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
99 unsigned Op0, unsigned Op1, uint64_t Imm);
101 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
102 /// to emit an instruction with an immediate operand using FastEmit_ri.
103 /// If that fails, it materializes the immediate into a register and try
104 /// FastEmit_rr instead.
105 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
106 ISD::NodeType Opcode,
107 unsigned Op0, uint64_t Imm,
108 MVT::SimpleValueType ImmType);
110 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
111 /// result register in the given register class.
113 unsigned FastEmitInst_(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC);
116 /// FastEmitInst_r - Emit a MachineInstr with one register operand
117 /// and a result register in the given register class.
119 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
120 const TargetRegisterClass *RC,
123 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
124 /// and a result register in the given register class.
126 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
127 const TargetRegisterClass *RC,
128 unsigned Op0, unsigned Op1);
130 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
131 /// and a result register in the given register class.
133 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
134 const TargetRegisterClass *RC,
135 unsigned Op0, uint64_t Imm);
137 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
138 /// an immediate, and a result register in the given register class.
140 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
141 const TargetRegisterClass *RC,
142 unsigned Op0, unsigned Op1, uint64_t Imm);
145 unsigned createResultReg(const TargetRegisterClass *RC);
147 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
148 DenseMap<const Value*, unsigned> &ValueMap);
150 bool SelectGetElementPtr(Instruction *I,
151 DenseMap<const Value*, unsigned> &ValueMap);