1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
28 class FunctionLoweringInfo;
30 class MachineBasicBlock;
31 class MachineConstantPool;
32 class MachineFunction;
34 class MachineFrameInfo;
35 class MachineRegisterInfo;
37 class TargetInstrInfo;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
44 /// FastISel - This is a fast-path instruction selection class that
45 /// generates poor code and doesn't support illegal types or non-trivial
46 /// lowering, but runs quickly.
49 DenseMap<const Value *, unsigned> LocalValueMap;
50 FunctionLoweringInfo &FuncInfo;
51 MachineRegisterInfo &MRI;
52 MachineFrameInfo &MFI;
53 MachineConstantPool &MCP;
55 const TargetMachine &TM;
57 const TargetInstrInfo &TII;
58 const TargetLowering &TLI;
59 const TargetRegisterInfo &TRI;
60 MachineInstr *LastLocalValue;
63 /// getLastLocalValue - Return the position of the last instruction
64 /// emitted for materializing constants for use in the current block.
65 MachineInstr *getLastLocalValue() { return LastLocalValue; }
67 /// setLastLocalValue - Update the position of the last instruction
68 /// emitted for materializing constants for use in the current block.
69 void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
71 /// startNewBlock - Set the current block to which generated machine
72 /// instructions will be appended, and clear the local CSE map.
76 /// getCurDebugLoc() - Return current debug location information.
77 DebugLoc getCurDebugLoc() const { return DL; }
79 /// SelectInstruction - Do "fast" instruction selection for the given
80 /// LLVM IR instruction, and append generated machine instructions to
81 /// the current block. Return true if selection was successful.
83 bool SelectInstruction(const Instruction *I);
85 /// SelectOperator - Do "fast" instruction selection for the given
86 /// LLVM IR operator (Instruction or ConstantExpr), and append
87 /// generated machine instructions to the current block. Return true
88 /// if selection was successful.
90 bool SelectOperator(const User *I, unsigned Opcode);
92 /// getRegForValue - Create a virtual register and arrange for it to
93 /// be assigned the value for the given LLVM value.
94 unsigned getRegForValue(const Value *V);
96 /// lookUpRegForValue - Look up the value to see if its value is already
97 /// cached in a register. It may be defined by instructions across blocks or
99 unsigned lookUpRegForValue(const Value *V);
101 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
102 /// takes care of truncating or sign-extending the given getelementptr
104 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
106 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
107 /// vreg is being provided by the specified load instruction. If possible,
108 /// try to fold the load as an operand to the instruction, returning true if
110 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/,
111 const LoadInst * /*LI*/) {
115 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
116 /// into the current block.
117 void recomputeInsertPt();
120 MachineBasicBlock::iterator InsertPt;
124 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
125 /// into the local value area and return the old insert position.
126 SavePoint enterLocalValueArea();
128 /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
129 void leaveLocalValueArea(SavePoint Old);
134 explicit FastISel(FunctionLoweringInfo &funcInfo);
136 /// TargetSelectInstruction - This method is called by target-independent
137 /// code when the normal FastISel process fails to select an instruction.
138 /// This gives targets a chance to emit code for anything that doesn't
139 /// fit into FastISel's framework. It returns true if it was successful.
142 TargetSelectInstruction(const Instruction *I) = 0;
144 /// FastEmit_r - This method is called by target-independent code
145 /// to request that an instruction with the given type and opcode
147 virtual unsigned FastEmit_(MVT VT,
151 /// FastEmit_r - This method is called by target-independent code
152 /// to request that an instruction with the given type, opcode, and
153 /// register operand be emitted.
155 virtual unsigned FastEmit_r(MVT VT,
158 unsigned Op0, bool Op0IsKill);
160 /// FastEmit_rr - This method is called by target-independent code
161 /// to request that an instruction with the given type, opcode, and
162 /// register operands be emitted.
164 virtual unsigned FastEmit_rr(MVT VT,
167 unsigned Op0, bool Op0IsKill,
168 unsigned Op1, bool Op1IsKill);
170 /// FastEmit_ri - This method is called by target-independent code
171 /// to request that an instruction with the given type, opcode, and
172 /// register and immediate operands be emitted.
174 virtual unsigned FastEmit_ri(MVT VT,
177 unsigned Op0, bool Op0IsKill,
180 /// FastEmit_rf - This method is called by target-independent code
181 /// to request that an instruction with the given type, opcode, and
182 /// register and floating-point immediate operands be emitted.
184 virtual unsigned FastEmit_rf(MVT VT,
187 unsigned Op0, bool Op0IsKill,
188 const ConstantFP *FPImm);
190 /// FastEmit_rri - This method is called by target-independent code
191 /// to request that an instruction with the given type, opcode, and
192 /// register and immediate operands be emitted.
194 virtual unsigned FastEmit_rri(MVT VT,
197 unsigned Op0, bool Op0IsKill,
198 unsigned Op1, bool Op1IsKill,
201 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
202 /// to emit an instruction with an immediate operand using FastEmit_ri.
203 /// If that fails, it materializes the immediate into a register and try
204 /// FastEmit_rr instead.
205 unsigned FastEmit_ri_(MVT VT,
207 unsigned Op0, bool Op0IsKill,
208 uint64_t Imm, MVT ImmType);
210 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
211 /// to emit an instruction with an immediate operand using FastEmit_rf.
212 /// If that fails, it materializes the immediate into a register and try
213 /// FastEmit_rr instead.
214 unsigned FastEmit_rf_(MVT VT,
216 unsigned Op0, bool Op0IsKill,
217 const ConstantFP *FPImm, MVT ImmType);
219 /// FastEmit_i - This method is called by target-independent code
220 /// to request that an instruction with the given type, opcode, and
221 /// immediate operand be emitted.
222 virtual unsigned FastEmit_i(MVT VT,
227 /// FastEmit_f - This method is called by target-independent code
228 /// to request that an instruction with the given type, opcode, and
229 /// floating-point immediate operand be emitted.
230 virtual unsigned FastEmit_f(MVT VT,
233 const ConstantFP *FPImm);
235 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
236 /// result register in the given register class.
238 unsigned FastEmitInst_(unsigned MachineInstOpcode,
239 const TargetRegisterClass *RC);
241 /// FastEmitInst_r - Emit a MachineInstr with one register operand
242 /// and a result register in the given register class.
244 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
245 const TargetRegisterClass *RC,
246 unsigned Op0, bool Op0IsKill);
248 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
249 /// and a result register in the given register class.
251 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
252 const TargetRegisterClass *RC,
253 unsigned Op0, bool Op0IsKill,
254 unsigned Op1, bool Op1IsKill);
256 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
257 /// and a result register in the given register class.
259 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
260 const TargetRegisterClass *RC,
261 unsigned Op0, bool Op0IsKill,
264 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
265 /// and a result register in the given register class.
267 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
268 const TargetRegisterClass *RC,
269 unsigned Op0, bool Op0IsKill,
270 const ConstantFP *FPImm);
272 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
273 /// an immediate, and a result register in the given register class.
275 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
276 const TargetRegisterClass *RC,
277 unsigned Op0, bool Op0IsKill,
278 unsigned Op1, bool Op1IsKill,
281 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
282 /// operand, and a result register in the given register class.
283 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
284 const TargetRegisterClass *RC,
287 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
288 /// from a specified index of a superregister to a specified type.
289 unsigned FastEmitInst_extractsubreg(MVT RetVT,
290 unsigned Op0, bool Op0IsKill,
293 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
294 /// with all but the least significant bit set to zero.
295 unsigned FastEmitZExtFromI1(MVT VT,
296 unsigned Op0, bool Op0IsKill);
298 /// FastEmitBranch - Emit an unconditional branch to the given block,
299 /// unless it is the immediate (fall-through) successor, and update
301 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
303 unsigned UpdateValueMap(const Value* I, unsigned Reg);
305 unsigned createResultReg(const TargetRegisterClass *RC);
307 /// TargetMaterializeConstant - Emit a constant in a register using
308 /// target-specific logic, such as constant pool loads.
309 virtual unsigned TargetMaterializeConstant(const Constant* C) {
313 /// TargetMaterializeAlloca - Emit an alloca address in a register using
314 /// target-specific logic.
315 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
320 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
322 bool SelectFNeg(const User *I);
324 bool SelectGetElementPtr(const User *I);
326 bool SelectCall(const User *I);
328 bool SelectBitCast(const User *I);
330 bool SelectCast(const User *I, unsigned Opcode);
332 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
333 /// Emit code to ensure constants are copied into registers when needed.
334 /// Remember the virtual registers that need to be added to the Machine PHI
335 /// nodes as input. We cannot just directly add them, because expansion
336 /// might result in multiple MBB's for one BB. As such, the start of the
337 /// BB might correspond to a different MBB than the end.
338 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
340 /// materializeRegForValue - Helper for getRegForVale. This function is
341 /// called when the value isn't already available in a register and must
342 /// be materialized with new instructions.
343 unsigned materializeRegForValue(const Value *V, MVT VT);
345 /// hasTrivialKill - Test whether the given value has exactly one use.
346 bool hasTrivialKill(const Value *V) const;