1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class MachineBasicBlock;
26 class MachineConstantPool;
27 class MachineFunction;
28 class MachineFrameInfo;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetInstrInfo;
35 class TargetRegisterClass;
37 /// FastISel - This is a fast-path instruction selection class that
38 /// generates poor code and doesn't support illegal types or non-trivial
39 /// lowering, but runs quickly.
42 MachineBasicBlock *MBB;
43 DenseMap<const Value *, unsigned> LocalValueMap;
44 DenseMap<const Value *, unsigned> &ValueMap;
45 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
46 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
48 MachineModuleInfo *MMI;
49 MachineRegisterInfo &MRI;
50 MachineFrameInfo &MFI;
51 MachineConstantPool &MCP;
52 const TargetMachine &TM;
54 const TargetInstrInfo &TII;
55 const TargetLowering &TLI;
58 /// setCurrentBlock - Set the current block, to which generated
59 /// machine instructions will be appended.
61 void setCurrentBlock(MachineBasicBlock *mbb) {
65 /// SelectInstruction - Do "fast" instruction selection for the given
66 /// LLVM IR instruction, and append generated machine instructions to
67 /// the current block. Return true if selection was successful.
69 bool SelectInstruction(Instruction *I);
71 /// SelectInstruction - Do "fast" instruction selection for the given
72 /// LLVM IR operator (Instruction or ConstantExpr), and append
73 /// generated machine instructions to the current block. Return true
74 /// if selection was successful.
76 bool SelectOperator(User *I, unsigned Opcode);
78 /// TargetSelectInstruction - This method is called by target-independent
79 /// code when the normal FastISel process fails to select an instruction.
80 /// This gives targets a chance to emit code for anything that doesn't
81 /// fit into FastISel's framework. It returns true if it was successful.
84 TargetSelectInstruction(Instruction *I) = 0;
86 /// getRegForValue - Create a virtual register and arrange for it to
87 /// be assigned the value for the given LLVM value.
88 unsigned getRegForValue(Value *V);
90 /// lookUpRegForValue - Look up the value to see if its value is already
91 /// cached in a register. It may be defined by instructions across blocks or
93 unsigned lookUpRegForValue(Value *V);
98 FastISel(MachineFunction &mf,
99 MachineModuleInfo *mmi,
100 DenseMap<const Value *, unsigned> &vm,
101 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
102 DenseMap<const AllocaInst *, int> &am);
104 /// FastEmit_r - This method is called by target-independent code
105 /// to request that an instruction with the given type and opcode
107 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
108 MVT::SimpleValueType RetVT,
109 ISD::NodeType Opcode);
111 /// FastEmit_r - This method is called by target-independent code
112 /// to request that an instruction with the given type, opcode, and
113 /// register operand be emitted.
115 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
116 MVT::SimpleValueType RetVT,
117 ISD::NodeType Opcode, unsigned Op0);
119 /// FastEmit_rr - This method is called by target-independent code
120 /// to request that an instruction with the given type, opcode, and
121 /// register operands be emitted.
123 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
124 MVT::SimpleValueType RetVT,
125 ISD::NodeType Opcode,
126 unsigned Op0, unsigned Op1);
128 /// FastEmit_ri - This method is called by target-independent code
129 /// to request that an instruction with the given type, opcode, and
130 /// register and immediate operands be emitted.
132 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
133 MVT::SimpleValueType RetVT,
134 ISD::NodeType Opcode,
135 unsigned Op0, uint64_t Imm);
137 /// FastEmit_rf - This method is called by target-independent code
138 /// to request that an instruction with the given type, opcode, and
139 /// register and floating-point immediate operands be emitted.
141 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
142 MVT::SimpleValueType RetVT,
143 ISD::NodeType Opcode,
144 unsigned Op0, ConstantFP *FPImm);
146 /// FastEmit_rri - This method is called by target-independent code
147 /// to request that an instruction with the given type, opcode, and
148 /// register and immediate operands be emitted.
150 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
151 MVT::SimpleValueType RetVT,
152 ISD::NodeType Opcode,
153 unsigned Op0, unsigned Op1, uint64_t Imm);
155 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
156 /// to emit an instruction with an immediate operand using FastEmit_ri.
157 /// If that fails, it materializes the immediate into a register and try
158 /// FastEmit_rr instead.
159 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
160 ISD::NodeType Opcode,
161 unsigned Op0, uint64_t Imm,
162 MVT::SimpleValueType ImmType);
164 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
165 /// to emit an instruction with an immediate operand using FastEmit_rf.
166 /// If that fails, it materializes the immediate into a register and try
167 /// FastEmit_rr instead.
168 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
169 ISD::NodeType Opcode,
170 unsigned Op0, ConstantFP *FPImm,
171 MVT::SimpleValueType ImmType);
173 /// FastEmit_i - This method is called by target-independent code
174 /// to request that an instruction with the given type, opcode, and
175 /// immediate operand be emitted.
176 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
177 MVT::SimpleValueType RetVT,
178 ISD::NodeType Opcode,
181 /// FastEmit_f - This method is called by target-independent code
182 /// to request that an instruction with the given type, opcode, and
183 /// floating-point immediate operand be emitted.
184 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
185 MVT::SimpleValueType RetVT,
186 ISD::NodeType Opcode,
189 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
190 /// result register in the given register class.
192 unsigned FastEmitInst_(unsigned MachineInstOpcode,
193 const TargetRegisterClass *RC);
195 /// FastEmitInst_r - Emit a MachineInstr with one register operand
196 /// and a result register in the given register class.
198 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
199 const TargetRegisterClass *RC,
202 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
203 /// and a result register in the given register class.
205 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC,
207 unsigned Op0, unsigned Op1);
209 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
210 /// and a result register in the given register class.
212 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
213 const TargetRegisterClass *RC,
214 unsigned Op0, uint64_t Imm);
216 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
217 /// and a result register in the given register class.
219 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
220 const TargetRegisterClass *RC,
221 unsigned Op0, ConstantFP *FPImm);
223 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
224 /// an immediate, and a result register in the given register class.
226 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC,
228 unsigned Op0, unsigned Op1, uint64_t Imm);
230 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
231 /// operand, and a result register in the given register class.
232 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
233 const TargetRegisterClass *RC,
236 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
237 /// from a specified index of a superregister.
238 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
240 void UpdateValueMap(Value* I, unsigned Reg);
242 unsigned createResultReg(const TargetRegisterClass *RC);
244 /// TargetMaterializeConstant - Emit a constant in a register using
245 /// target-specific logic, such as constant pool loads.
246 virtual unsigned TargetMaterializeConstant(Constant* C) {
250 /// TargetMaterializeAlloca - Emit an alloca address in a register using
251 /// target-specific logic.
252 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
257 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
259 bool SelectGetElementPtr(User *I);
261 bool SelectCall(User *I);
263 bool SelectBitCast(User *I);
265 bool SelectCast(User *I, ISD::NodeType Opcode);