1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MachineRegisterInfo;
27 class TargetInstrInfo;
29 class TargetRegisterClass;
31 /// FastISel - This is a fast-path instruction selection class that
32 /// generates poor code and doesn't support illegal types or non-trivial
33 /// lowering, but runs quickly.
35 MachineBasicBlock *MBB;
37 MachineRegisterInfo &MRI;
39 const TargetInstrInfo &TII;
43 /// SelectInstructions - Do "fast" instruction selection over the
44 /// LLVM IR instructions in the range [Begin, N) where N is either
45 /// End or the first unsupported instruction. Return N.
46 /// ValueMap is filled in with a mapping of LLVM IR Values to
49 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
50 DenseMap<const Value*, unsigned> &ValueMap,
51 MachineBasicBlock *mbb);
56 explicit FastISel(MachineFunction &mf);
58 /// FastEmit_r - This method is called by target-independent code
59 /// to request that an instruction with the given type and opcode
61 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
62 ISD::NodeType Opcode);
64 /// FastEmit_r - This method is called by target-independent code
65 /// to request that an instruction with the given type, opcode, and
66 /// register operand be emitted.
68 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
69 ISD::NodeType Opcode, unsigned Op0);
71 /// FastEmit_rr - This method is called by target-independent code
72 /// to request that an instruction with the given type, opcode, and
73 /// register operands be emitted.
75 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
77 unsigned Op0, unsigned Op1);
79 /// FastEmit_i - This method is called by target-independent code
80 /// to request that an instruction with the given type which materialize
81 /// the specified immediate value.
82 virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
84 /// FastEmit_ri - This method is called by target-independent code
85 /// to request that an instruction with the given type, opcode, and
86 /// register and immediate operands be emitted.
88 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
90 unsigned Op0, uint64_t Imm,
91 MVT::SimpleValueType ImmType);
93 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
94 /// to emit an instruction with an immediate operand using FastEmit_ri.
95 /// If that fails, it materializes the immediate into a register and try
96 /// FastEmit_rr instead.
97 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
99 unsigned Op0, uint64_t Imm,
100 MVT::SimpleValueType ImmType);
102 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
103 /// result register in the given register class.
105 unsigned FastEmitInst_(unsigned MachineInstOpcode,
106 const TargetRegisterClass *RC);
108 /// FastEmitInst_ - Emit a MachineInstr with one register operand
109 /// and a result register in the given register class.
111 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
115 /// FastEmitInst_ - Emit a MachineInstr with two register operands
116 /// and a result register in the given register class.
118 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, unsigned Op1);
123 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
124 DenseMap<const Value*, unsigned> &ValueMap);
126 bool SelectGetElementPtr(Instruction *I,
127 DenseMap<const Value*, unsigned> &ValueMap);