1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class MachineBasicBlock;
25 class MachineFunction;
26 class MachineRegisterInfo;
28 class TargetInstrInfo;
31 class TargetRegisterClass;
33 /// FastISel - This is a fast-path instruction selection class that
34 /// generates poor code and doesn't support illegal types or non-trivial
35 /// lowering, but runs quickly.
38 MachineBasicBlock *MBB;
40 MachineRegisterInfo &MRI;
41 const TargetMachine &TM;
43 const TargetInstrInfo &TII;
44 const TargetLowering &TLI;
47 /// SelectInstructions - Do "fast" instruction selection over the
48 /// LLVM IR instructions in the range [Begin, N) where N is either
49 /// End or the first unsupported instruction. Return N.
50 /// ValueMap is filled in with a mapping of LLVM IR Values to
51 /// virtual register numbers. MBB is a block to which to append
52 /// the generated MachineInstrs.
54 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
55 DenseMap<const Value*, unsigned> &ValueMap,
56 DenseMap<const BasicBlock*, MachineBasicBlock *> &MBBMap,
57 MachineBasicBlock *MBB);
62 explicit FastISel(MachineFunction &mf);
64 /// FastEmit_r - This method is called by target-independent code
65 /// to request that an instruction with the given type and opcode
67 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
68 MVT::SimpleValueType RetVT,
69 ISD::NodeType Opcode);
71 /// FastEmit_r - This method is called by target-independent code
72 /// to request that an instruction with the given type, opcode, and
73 /// register operand be emitted.
75 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
76 MVT::SimpleValueType RetVT,
77 ISD::NodeType Opcode, unsigned Op0);
79 /// FastEmit_rr - This method is called by target-independent code
80 /// to request that an instruction with the given type, opcode, and
81 /// register operands be emitted.
83 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
84 MVT::SimpleValueType RetVT,
86 unsigned Op0, unsigned Op1);
88 /// FastEmit_ri - This method is called by target-independent code
89 /// to request that an instruction with the given type, opcode, and
90 /// register and immediate operands be emitted.
92 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
93 MVT::SimpleValueType RetVT,
95 unsigned Op0, uint64_t Imm);
97 /// FastEmit_rf - This method is called by target-independent code
98 /// to request that an instruction with the given type, opcode, and
99 /// register and floating-point immediate operands be emitted.
101 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
102 MVT::SimpleValueType RetVT,
103 ISD::NodeType Opcode,
104 unsigned Op0, ConstantFP *FPImm);
106 /// FastEmit_rri - This method is called by target-independent code
107 /// to request that an instruction with the given type, opcode, and
108 /// register and immediate operands be emitted.
110 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
111 MVT::SimpleValueType RetVT,
112 ISD::NodeType Opcode,
113 unsigned Op0, unsigned Op1, uint64_t Imm);
115 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
116 /// to emit an instruction with an immediate operand using FastEmit_ri.
117 /// If that fails, it materializes the immediate into a register and try
118 /// FastEmit_rr instead.
119 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
120 ISD::NodeType Opcode,
121 unsigned Op0, uint64_t Imm,
122 MVT::SimpleValueType ImmType);
124 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
125 /// to emit an instruction with an immediate operand using FastEmit_rf.
126 /// If that fails, it materializes the immediate into a register and try
127 /// FastEmit_rr instead.
128 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
129 ISD::NodeType Opcode,
130 unsigned Op0, ConstantFP *FPImm,
131 MVT::SimpleValueType ImmType);
133 /// FastEmit_i - This method is called by target-independent code
134 /// to request that an instruction with the given type, opcode, and
135 /// immediate operand be emitted.
136 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
137 MVT::SimpleValueType RetVT,
138 ISD::NodeType Opcode,
141 /// FastEmit_f - This method is called by target-independent code
142 /// to request that an instruction with the given type, opcode, and
143 /// floating-point immediate operand be emitted.
144 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
145 MVT::SimpleValueType RetVT,
146 ISD::NodeType Opcode,
149 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
150 /// result register in the given register class.
152 unsigned FastEmitInst_(unsigned MachineInstOpcode,
153 const TargetRegisterClass *RC);
155 /// FastEmitInst_r - Emit a MachineInstr with one register operand
156 /// and a result register in the given register class.
158 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
159 const TargetRegisterClass *RC,
162 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
163 /// and a result register in the given register class.
165 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
166 const TargetRegisterClass *RC,
167 unsigned Op0, unsigned Op1);
169 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
170 /// and a result register in the given register class.
172 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
173 const TargetRegisterClass *RC,
174 unsigned Op0, uint64_t Imm);
176 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
177 /// and a result register in the given register class.
179 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
180 const TargetRegisterClass *RC,
181 unsigned Op0, ConstantFP *FPImm);
183 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
184 /// an immediate, and a result register in the given register class.
186 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
187 const TargetRegisterClass *RC,
188 unsigned Op0, unsigned Op1, uint64_t Imm);
190 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
191 /// operand, and a result register in the given register class.
192 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
193 const TargetRegisterClass *RC,
196 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
197 /// from a specified index of a superregister.
198 unsigned FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
199 unsigned Op0, uint32_t Idx);
202 unsigned getRegForValue(Value *V,
203 DenseMap<const Value*, unsigned> &ValueMap);
205 unsigned createResultReg(const TargetRegisterClass *RC);
207 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
208 DenseMap<const Value*, unsigned> &ValueMap);
210 bool SelectGetElementPtr(Instruction *I,
211 DenseMap<const Value*, unsigned> &ValueMap);
213 bool SelectBitCast(Instruction *I,
214 DenseMap<const Value*, unsigned> &ValueMap);
216 bool SelectCast(Instruction *I, ISD::NodeType Opcode,
217 DenseMap<const Value*, unsigned> &ValueMap);