1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/DebugLoc.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineFrameInfo;
31 class MachineModuleInfo;
33 class MachineRegisterInfo;
35 class TargetInstrInfo;
38 class TargetRegisterClass;
40 /// FastISel - This is a fast-path instruction selection class that
41 /// generates poor code and doesn't support illegal types or non-trivial
42 /// lowering, but runs quickly.
45 MachineBasicBlock *MBB;
46 DenseMap<const Value *, unsigned> LocalValueMap;
47 DenseMap<const Value *, unsigned> &ValueMap;
48 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
49 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
51 SmallSet<Instruction*, 8> &CatchInfoLost;
54 MachineModuleInfo *MMI;
56 MachineRegisterInfo &MRI;
57 MachineFrameInfo &MFI;
58 MachineConstantPool &MCP;
60 const TargetMachine &TM;
62 const TargetInstrInfo &TII;
63 const TargetLowering &TLI;
66 /// startNewBlock - Set the current block to which generated machine
67 /// instructions will be appended, and clear the local CSE map.
69 void startNewBlock(MachineBasicBlock *mbb) {
71 LocalValueMap.clear();
74 /// setCurrentBlock - Set the current block to which generated machine
75 /// instructions will be appended.
77 void setCurrentBlock(MachineBasicBlock *mbb) {
81 /// setCurDebugLoc - Set the current debug location information, which is used
82 /// when creating a machine instruction.
84 void setCurDebugLoc(DebugLoc dl) { DL = dl; }
86 /// SelectInstruction - Do "fast" instruction selection for the given
87 /// LLVM IR instruction, and append generated machine instructions to
88 /// the current block. Return true if selection was successful.
90 bool SelectInstruction(Instruction *I);
92 /// SelectInstruction - Do "fast" instruction selection for the given
93 /// LLVM IR operator (Instruction or ConstantExpr), and append
94 /// generated machine instructions to the current block. Return true
95 /// if selection was successful.
97 bool SelectOperator(User *I, unsigned Opcode);
99 /// TargetSelectInstruction - This method is called by target-independent
100 /// code when the normal FastISel process fails to select an instruction.
101 /// This gives targets a chance to emit code for anything that doesn't
102 /// fit into FastISel's framework. It returns true if it was successful.
105 TargetSelectInstruction(Instruction *I) = 0;
107 /// getRegForValue - Create a virtual register and arrange for it to
108 /// be assigned the value for the given LLVM value.
109 unsigned getRegForValue(Value *V);
111 /// lookUpRegForValue - Look up the value to see if its value is already
112 /// cached in a register. It may be defined by instructions across blocks or
114 unsigned lookUpRegForValue(Value *V);
116 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
117 /// takes care of truncating or sign-extending the given getelementptr
119 unsigned getRegForGEPIndex(Value *V);
124 FastISel(MachineFunction &mf,
125 MachineModuleInfo *mmi,
127 DenseMap<const Value *, unsigned> &vm,
128 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
129 DenseMap<const AllocaInst *, int> &am
131 , SmallSet<Instruction*, 8> &cil
135 /// FastEmit_r - This method is called by target-independent code
136 /// to request that an instruction with the given type and opcode
138 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
139 MVT::SimpleValueType RetVT,
140 ISD::NodeType Opcode);
142 /// FastEmit_r - This method is called by target-independent code
143 /// to request that an instruction with the given type, opcode, and
144 /// register operand be emitted.
146 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
147 MVT::SimpleValueType RetVT,
148 ISD::NodeType Opcode, unsigned Op0);
150 /// FastEmit_rr - This method is called by target-independent code
151 /// to request that an instruction with the given type, opcode, and
152 /// register operands be emitted.
154 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
155 MVT::SimpleValueType RetVT,
156 ISD::NodeType Opcode,
157 unsigned Op0, unsigned Op1);
159 /// FastEmit_ri - This method is called by target-independent code
160 /// to request that an instruction with the given type, opcode, and
161 /// register and immediate operands be emitted.
163 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
164 MVT::SimpleValueType RetVT,
165 ISD::NodeType Opcode,
166 unsigned Op0, uint64_t Imm);
168 /// FastEmit_rf - This method is called by target-independent code
169 /// to request that an instruction with the given type, opcode, and
170 /// register and floating-point immediate operands be emitted.
172 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
173 MVT::SimpleValueType RetVT,
174 ISD::NodeType Opcode,
175 unsigned Op0, ConstantFP *FPImm);
177 /// FastEmit_rri - This method is called by target-independent code
178 /// to request that an instruction with the given type, opcode, and
179 /// register and immediate operands be emitted.
181 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
182 MVT::SimpleValueType RetVT,
183 ISD::NodeType Opcode,
184 unsigned Op0, unsigned Op1, uint64_t Imm);
186 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
187 /// to emit an instruction with an immediate operand using FastEmit_ri.
188 /// If that fails, it materializes the immediate into a register and try
189 /// FastEmit_rr instead.
190 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
191 ISD::NodeType Opcode,
192 unsigned Op0, uint64_t Imm,
193 MVT::SimpleValueType ImmType);
195 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
196 /// to emit an instruction with an immediate operand using FastEmit_rf.
197 /// If that fails, it materializes the immediate into a register and try
198 /// FastEmit_rr instead.
199 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
200 ISD::NodeType Opcode,
201 unsigned Op0, ConstantFP *FPImm,
202 MVT::SimpleValueType ImmType);
204 /// FastEmit_i - This method is called by target-independent code
205 /// to request that an instruction with the given type, opcode, and
206 /// immediate operand be emitted.
207 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
208 MVT::SimpleValueType RetVT,
209 ISD::NodeType Opcode,
212 /// FastEmit_f - This method is called by target-independent code
213 /// to request that an instruction with the given type, opcode, and
214 /// floating-point immediate operand be emitted.
215 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
216 MVT::SimpleValueType RetVT,
217 ISD::NodeType Opcode,
220 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
221 /// result register in the given register class.
223 unsigned FastEmitInst_(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC);
226 /// FastEmitInst_r - Emit a MachineInstr with one register operand
227 /// and a result register in the given register class.
229 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
230 const TargetRegisterClass *RC,
233 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
234 /// and a result register in the given register class.
236 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
237 const TargetRegisterClass *RC,
238 unsigned Op0, unsigned Op1);
240 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
241 /// and a result register in the given register class.
243 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
244 const TargetRegisterClass *RC,
245 unsigned Op0, uint64_t Imm);
247 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
248 /// and a result register in the given register class.
250 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
251 const TargetRegisterClass *RC,
252 unsigned Op0, ConstantFP *FPImm);
254 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
255 /// an immediate, and a result register in the given register class.
257 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
258 const TargetRegisterClass *RC,
259 unsigned Op0, unsigned Op1, uint64_t Imm);
261 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
262 /// operand, and a result register in the given register class.
263 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
264 const TargetRegisterClass *RC,
267 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
268 /// from a specified index of a superregister to a specified type.
269 unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
270 unsigned Op0, uint32_t Idx);
272 /// FastEmitBranch - Emit an unconditional branch to the given block,
273 /// unless it is the immediate (fall-through) successor, and update
275 void FastEmitBranch(MachineBasicBlock *MBB);
277 void UpdateValueMap(Value* I, unsigned Reg);
279 unsigned createResultReg(const TargetRegisterClass *RC);
281 /// TargetMaterializeConstant - Emit a constant in a register using
282 /// target-specific logic, such as constant pool loads.
283 virtual unsigned TargetMaterializeConstant(Constant* C) {
287 /// TargetMaterializeAlloca - Emit an alloca address in a register using
288 /// target-specific logic.
289 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
294 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
296 bool SelectGetElementPtr(User *I);
298 bool SelectCall(User *I);
300 bool SelectBitCast(User *I);
302 bool SelectCast(User *I, ISD::NodeType Opcode);