1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 class MachineBasicBlock;
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineFrameInfo;
30 class MachineModuleInfo;
31 class MachineRegisterInfo;
33 class TargetInstrInfo;
36 class TargetRegisterClass;
38 /// FastISel - This is a fast-path instruction selection class that
39 /// generates poor code and doesn't support illegal types or non-trivial
40 /// lowering, but runs quickly.
43 MachineBasicBlock *MBB;
44 DenseMap<const Value *, unsigned> LocalValueMap;
45 DenseMap<const Value *, unsigned> &ValueMap;
46 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
47 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
49 SmallSet<Instruction*, 8> &CatchInfoLost;
52 MachineModuleInfo *MMI;
53 MachineRegisterInfo &MRI;
54 MachineFrameInfo &MFI;
55 MachineConstantPool &MCP;
57 const TargetMachine &TM;
59 const TargetInstrInfo &TII;
60 const TargetLowering &TLI;
63 /// startNewBlock - Set the current block to which generated machine
64 /// instructions will be appended, and clear the local CSE map.
66 void startNewBlock(MachineBasicBlock *mbb) {
68 LocalValueMap.clear();
71 /// setCurrentBlock - Set the current block to which generated machine
72 /// instructions will be appended.
74 void setCurrentBlock(MachineBasicBlock *mbb) {
78 /// setCurDebugLoc - Set the current debug location information, which is used
79 /// when creating a machine instruction.
81 void setCurDebugLoc(DebugLoc dl) { DL = dl; }
83 /// getCurDebugLoc() - Return current debug location information.
84 DebugLoc getCurDebugLoc() const { return DL; }
86 /// SelectInstruction - Do "fast" instruction selection for the given
87 /// LLVM IR instruction, and append generated machine instructions to
88 /// the current block. Return true if selection was successful.
90 bool SelectInstruction(Instruction *I);
92 /// SelectOperator - Do "fast" instruction selection for the given
93 /// LLVM IR operator (Instruction or ConstantExpr), and append
94 /// generated machine instructions to the current block. Return true
95 /// if selection was successful.
97 bool SelectOperator(User *I, unsigned Opcode);
99 /// getRegForValue - Create a virtual register and arrange for it to
100 /// be assigned the value for the given LLVM value.
101 unsigned getRegForValue(Value *V);
103 /// lookUpRegForValue - Look up the value to see if its value is already
104 /// cached in a register. It may be defined by instructions across blocks or
106 unsigned lookUpRegForValue(Value *V);
108 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
109 /// takes care of truncating or sign-extending the given getelementptr
111 unsigned getRegForGEPIndex(Value *V);
116 FastISel(MachineFunction &mf,
117 MachineModuleInfo *mmi,
118 DenseMap<const Value *, unsigned> &vm,
119 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
120 DenseMap<const AllocaInst *, int> &am
122 , SmallSet<Instruction*, 8> &cil
126 /// TargetSelectInstruction - This method is called by target-independent
127 /// code when the normal FastISel process fails to select an instruction.
128 /// This gives targets a chance to emit code for anything that doesn't
129 /// fit into FastISel's framework. It returns true if it was successful.
132 TargetSelectInstruction(Instruction *I) = 0;
134 /// FastEmit_r - This method is called by target-independent code
135 /// to request that an instruction with the given type and opcode
137 virtual unsigned FastEmit_(MVT VT,
141 /// FastEmit_r - This method is called by target-independent code
142 /// to request that an instruction with the given type, opcode, and
143 /// register operand be emitted.
145 virtual unsigned FastEmit_r(MVT VT,
147 unsigned Opcode, unsigned Op0);
149 /// FastEmit_rr - This method is called by target-independent code
150 /// to request that an instruction with the given type, opcode, and
151 /// register operands be emitted.
153 virtual unsigned FastEmit_rr(MVT VT,
156 unsigned Op0, unsigned Op1);
158 /// FastEmit_ri - This method is called by target-independent code
159 /// to request that an instruction with the given type, opcode, and
160 /// register and immediate operands be emitted.
162 virtual unsigned FastEmit_ri(MVT VT,
165 unsigned Op0, uint64_t Imm);
167 /// FastEmit_rf - This method is called by target-independent code
168 /// to request that an instruction with the given type, opcode, and
169 /// register and floating-point immediate operands be emitted.
171 virtual unsigned FastEmit_rf(MVT VT,
174 unsigned Op0, ConstantFP *FPImm);
176 /// FastEmit_rri - This method is called by target-independent code
177 /// to request that an instruction with the given type, opcode, and
178 /// register and immediate operands be emitted.
180 virtual unsigned FastEmit_rri(MVT VT,
183 unsigned Op0, unsigned Op1, uint64_t Imm);
185 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
186 /// to emit an instruction with an immediate operand using FastEmit_ri.
187 /// If that fails, it materializes the immediate into a register and try
188 /// FastEmit_rr instead.
189 unsigned FastEmit_ri_(MVT VT,
191 unsigned Op0, uint64_t Imm,
194 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
195 /// to emit an instruction with an immediate operand using FastEmit_rf.
196 /// If that fails, it materializes the immediate into a register and try
197 /// FastEmit_rr instead.
198 unsigned FastEmit_rf_(MVT VT,
200 unsigned Op0, ConstantFP *FPImm,
203 /// FastEmit_i - This method is called by target-independent code
204 /// to request that an instruction with the given type, opcode, and
205 /// immediate operand be emitted.
206 virtual unsigned FastEmit_i(MVT VT,
211 /// FastEmit_f - This method is called by target-independent code
212 /// to request that an instruction with the given type, opcode, and
213 /// floating-point immediate operand be emitted.
214 virtual unsigned FastEmit_f(MVT VT,
219 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
220 /// result register in the given register class.
222 unsigned FastEmitInst_(unsigned MachineInstOpcode,
223 const TargetRegisterClass *RC);
225 /// FastEmitInst_r - Emit a MachineInstr with one register operand
226 /// and a result register in the given register class.
228 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
229 const TargetRegisterClass *RC,
232 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
233 /// and a result register in the given register class.
235 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC,
237 unsigned Op0, unsigned Op1);
239 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
240 /// and a result register in the given register class.
242 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
243 const TargetRegisterClass *RC,
244 unsigned Op0, uint64_t Imm);
246 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
247 /// and a result register in the given register class.
249 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
250 const TargetRegisterClass *RC,
251 unsigned Op0, ConstantFP *FPImm);
253 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
254 /// an immediate, and a result register in the given register class.
256 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
257 const TargetRegisterClass *RC,
258 unsigned Op0, unsigned Op1, uint64_t Imm);
260 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
261 /// operand, and a result register in the given register class.
262 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
263 const TargetRegisterClass *RC,
266 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
267 /// from a specified index of a superregister to a specified type.
268 unsigned FastEmitInst_extractsubreg(MVT RetVT,
269 unsigned Op0, uint32_t Idx);
271 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
272 /// with all but the least significant bit set to zero.
273 unsigned FastEmitZExtFromI1(MVT VT,
276 /// FastEmitBranch - Emit an unconditional branch to the given block,
277 /// unless it is the immediate (fall-through) successor, and update
279 void FastEmitBranch(MachineBasicBlock *MBB);
281 unsigned UpdateValueMap(Value* I, unsigned Reg);
283 unsigned createResultReg(const TargetRegisterClass *RC);
285 /// TargetMaterializeConstant - Emit a constant in a register using
286 /// target-specific logic, such as constant pool loads.
287 virtual unsigned TargetMaterializeConstant(Constant* C) {
291 /// TargetMaterializeAlloca - Emit an alloca address in a register using
292 /// target-specific logic.
293 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
298 bool SelectBinaryOp(User *I, unsigned ISDOpcode);
300 bool SelectFNeg(User *I);
302 bool SelectGetElementPtr(User *I);
304 bool SelectCall(User *I);
306 bool SelectBitCast(User *I);
308 bool SelectCast(User *I, unsigned Opcode);