1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
27 class FunctionLoweringInfo;
29 class MachineBasicBlock;
30 class MachineConstantPool;
31 class MachineFunction;
33 class MachineFrameInfo;
34 class MachineRegisterInfo;
36 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
42 /// FastISel - This is a fast-path instruction selection class that
43 /// generates poor code and doesn't support illegal types or non-trivial
44 /// lowering, but runs quickly.
47 DenseMap<const Value *, unsigned> LocalValueMap;
48 FunctionLoweringInfo &FuncInfo;
49 MachineRegisterInfo &MRI;
50 MachineFrameInfo &MFI;
51 MachineConstantPool &MCP;
53 const TargetMachine &TM;
55 const TargetInstrInfo &TII;
56 const TargetLowering &TLI;
57 const TargetRegisterInfo &TRI;
61 /// startNewBlock - Set the current block to which generated machine
62 /// instructions will be appended, and clear the local CSE map.
64 void startNewBlock() {
65 LocalValueMap.clear();
68 /// getCurDebugLoc() - Return current debug location information.
69 DebugLoc getCurDebugLoc() const { return DL; }
71 /// SelectInstruction - Do "fast" instruction selection for the given
72 /// LLVM IR instruction, and append generated machine instructions to
73 /// the current block. Return true if selection was successful.
75 bool SelectInstruction(const Instruction *I);
77 /// SelectOperator - Do "fast" instruction selection for the given
78 /// LLVM IR operator (Instruction or ConstantExpr), and append
79 /// generated machine instructions to the current block. Return true
80 /// if selection was successful.
82 bool SelectOperator(const User *I, unsigned Opcode);
84 /// getRegForValue - Create a virtual register and arrange for it to
85 /// be assigned the value for the given LLVM value.
86 unsigned getRegForValue(const Value *V);
88 /// lookUpRegForValue - Look up the value to see if its value is already
89 /// cached in a register. It may be defined by instructions across blocks or
91 unsigned lookUpRegForValue(const Value *V);
93 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
94 /// takes care of truncating or sign-extending the given getelementptr
96 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
101 explicit FastISel(FunctionLoweringInfo &funcInfo);
103 /// TargetSelectInstruction - This method is called by target-independent
104 /// code when the normal FastISel process fails to select an instruction.
105 /// This gives targets a chance to emit code for anything that doesn't
106 /// fit into FastISel's framework. It returns true if it was successful.
109 TargetSelectInstruction(const Instruction *I) = 0;
111 /// FastEmit_r - This method is called by target-independent code
112 /// to request that an instruction with the given type and opcode
114 virtual unsigned FastEmit_(MVT VT,
118 /// FastEmit_r - This method is called by target-independent code
119 /// to request that an instruction with the given type, opcode, and
120 /// register operand be emitted.
122 virtual unsigned FastEmit_r(MVT VT,
125 unsigned Op0, bool Op0IsKill);
127 /// FastEmit_rr - This method is called by target-independent code
128 /// to request that an instruction with the given type, opcode, and
129 /// register operands be emitted.
131 virtual unsigned FastEmit_rr(MVT VT,
134 unsigned Op0, bool Op0IsKill,
135 unsigned Op1, bool Op1IsKill);
137 /// FastEmit_ri - This method is called by target-independent code
138 /// to request that an instruction with the given type, opcode, and
139 /// register and immediate operands be emitted.
141 virtual unsigned FastEmit_ri(MVT VT,
144 unsigned Op0, bool Op0IsKill,
147 /// FastEmit_rf - This method is called by target-independent code
148 /// to request that an instruction with the given type, opcode, and
149 /// register and floating-point immediate operands be emitted.
151 virtual unsigned FastEmit_rf(MVT VT,
154 unsigned Op0, bool Op0IsKill,
155 const ConstantFP *FPImm);
157 /// FastEmit_rri - This method is called by target-independent code
158 /// to request that an instruction with the given type, opcode, and
159 /// register and immediate operands be emitted.
161 virtual unsigned FastEmit_rri(MVT VT,
164 unsigned Op0, bool Op0IsKill,
165 unsigned Op1, bool Op1IsKill,
168 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
169 /// to emit an instruction with an immediate operand using FastEmit_ri.
170 /// If that fails, it materializes the immediate into a register and try
171 /// FastEmit_rr instead.
172 unsigned FastEmit_ri_(MVT VT,
174 unsigned Op0, bool Op0IsKill,
175 uint64_t Imm, MVT ImmType);
177 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
178 /// to emit an instruction with an immediate operand using FastEmit_rf.
179 /// If that fails, it materializes the immediate into a register and try
180 /// FastEmit_rr instead.
181 unsigned FastEmit_rf_(MVT VT,
183 unsigned Op0, bool Op0IsKill,
184 const ConstantFP *FPImm, MVT ImmType);
186 /// FastEmit_i - This method is called by target-independent code
187 /// to request that an instruction with the given type, opcode, and
188 /// immediate operand be emitted.
189 virtual unsigned FastEmit_i(MVT VT,
194 /// FastEmit_f - This method is called by target-independent code
195 /// to request that an instruction with the given type, opcode, and
196 /// floating-point immediate operand be emitted.
197 virtual unsigned FastEmit_f(MVT VT,
200 const ConstantFP *FPImm);
202 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
203 /// result register in the given register class.
205 unsigned FastEmitInst_(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC);
208 /// FastEmitInst_r - Emit a MachineInstr with one register operand
209 /// and a result register in the given register class.
211 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
212 const TargetRegisterClass *RC,
213 unsigned Op0, bool Op0IsKill);
215 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
216 /// and a result register in the given register class.
218 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
219 const TargetRegisterClass *RC,
220 unsigned Op0, bool Op0IsKill,
221 unsigned Op1, bool Op1IsKill);
223 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
224 /// and a result register in the given register class.
226 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC,
228 unsigned Op0, bool Op0IsKill,
231 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
232 /// and a result register in the given register class.
234 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
235 const TargetRegisterClass *RC,
236 unsigned Op0, bool Op0IsKill,
237 const ConstantFP *FPImm);
239 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
240 /// an immediate, and a result register in the given register class.
242 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
243 const TargetRegisterClass *RC,
244 unsigned Op0, bool Op0IsKill,
245 unsigned Op1, bool Op1IsKill,
248 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
249 /// operand, and a result register in the given register class.
250 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
251 const TargetRegisterClass *RC,
254 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
255 /// from a specified index of a superregister to a specified type.
256 unsigned FastEmitInst_extractsubreg(MVT RetVT,
257 unsigned Op0, bool Op0IsKill,
260 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
261 /// with all but the least significant bit set to zero.
262 unsigned FastEmitZExtFromI1(MVT VT,
263 unsigned Op0, bool Op0IsKill);
265 /// FastEmitBranch - Emit an unconditional branch to the given block,
266 /// unless it is the immediate (fall-through) successor, and update
268 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
270 unsigned UpdateValueMap(const Value* I, unsigned Reg);
272 unsigned createResultReg(const TargetRegisterClass *RC);
274 /// TargetMaterializeConstant - Emit a constant in a register using
275 /// target-specific logic, such as constant pool loads.
276 virtual unsigned TargetMaterializeConstant(const Constant* C) {
280 /// TargetMaterializeAlloca - Emit an alloca address in a register using
281 /// target-specific logic.
282 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
287 bool SelectLoad(const User *I);
289 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
291 bool SelectFNeg(const User *I);
293 bool SelectGetElementPtr(const User *I);
295 bool SelectCall(const User *I);
297 bool SelectBitCast(const User *I);
299 bool SelectCast(const User *I, unsigned Opcode);
301 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
302 /// Emit code to ensure constants are copied into registers when needed.
303 /// Remember the virtual registers that need to be added to the Machine PHI
304 /// nodes as input. We cannot just directly add them, because expansion
305 /// might result in multiple MBB's for one BB. As such, the start of the
306 /// BB might correspond to a different MBB than the end.
307 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
309 /// materializeRegForValue - Helper for getRegForVale. This function is
310 /// called when the value isn't already available in a register and must
311 /// be materialized with new instructions.
312 unsigned materializeRegForValue(const Value *V, MVT VT);
314 /// hasTrivialKill - Test whether the given value has exactly one use.
315 bool hasTrivialKill(const Value *V) const;