1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineBasicBlock;
29 class MachineConstantPool;
30 class MachineFunction;
32 class MachineFrameInfo;
33 class MachineRegisterInfo;
35 class TargetInstrInfo;
38 class TargetRegisterClass;
40 /// FastISel - This is a fast-path instruction selection class that
41 /// generates poor code and doesn't support illegal types or non-trivial
42 /// lowering, but runs quickly.
45 MachineBasicBlock *MBB;
46 DenseMap<const Value *, unsigned> LocalValueMap;
47 DenseMap<const Value *, unsigned> &ValueMap;
48 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
49 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
52 SmallSet<const Instruction *, 8> &CatchInfoLost;
55 MachineRegisterInfo &MRI;
56 MachineFrameInfo &MFI;
57 MachineConstantPool &MCP;
59 const TargetMachine &TM;
61 const TargetInstrInfo &TII;
62 const TargetLowering &TLI;
65 /// startNewBlock - Set the current block to which generated machine
66 /// instructions will be appended, and clear the local CSE map.
68 void startNewBlock(MachineBasicBlock *mbb) {
70 LocalValueMap.clear();
73 /// setCurrentBlock - Set the current block to which generated machine
74 /// instructions will be appended.
76 void setCurrentBlock(MachineBasicBlock *mbb) {
80 /// getCurDebugLoc() - Return current debug location information.
81 DebugLoc getCurDebugLoc() const { return DL; }
83 /// SelectInstruction - Do "fast" instruction selection for the given
84 /// LLVM IR instruction, and append generated machine instructions to
85 /// the current block. Return true if selection was successful.
87 bool SelectInstruction(const Instruction *I);
89 /// SelectOperator - Do "fast" instruction selection for the given
90 /// LLVM IR operator (Instruction or ConstantExpr), and append
91 /// generated machine instructions to the current block. Return true
92 /// if selection was successful.
94 bool SelectOperator(const User *I, unsigned Opcode);
96 /// getRegForValue - Create a virtual register and arrange for it to
97 /// be assigned the value for the given LLVM value.
98 unsigned getRegForValue(const Value *V);
100 /// lookUpRegForValue - Look up the value to see if its value is already
101 /// cached in a register. It may be defined by instructions across blocks or
103 unsigned lookUpRegForValue(const Value *V);
105 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
106 /// takes care of truncating or sign-extending the given getelementptr
108 unsigned getRegForGEPIndex(const Value *V);
110 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
111 /// Emit code to ensure constants are copied into registers when needed.
112 /// Remember the virtual registers that need to be added to the Machine PHI
113 /// nodes as input. We cannot just directly add them, because expansion
114 /// might result in multiple MBB's for one BB. As such, the start of the
115 /// BB might correspond to a different MBB than the end.
116 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
121 FastISel(MachineFunction &mf,
122 DenseMap<const Value *, unsigned> &vm,
123 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
124 DenseMap<const AllocaInst *, int> &am,
125 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
127 , SmallSet<const Instruction *, 8> &cil
131 /// TargetSelectInstruction - This method is called by target-independent
132 /// code when the normal FastISel process fails to select an instruction.
133 /// This gives targets a chance to emit code for anything that doesn't
134 /// fit into FastISel's framework. It returns true if it was successful.
137 TargetSelectInstruction(const Instruction *I) = 0;
139 /// FastEmit_r - This method is called by target-independent code
140 /// to request that an instruction with the given type and opcode
142 virtual unsigned FastEmit_(MVT VT,
146 /// FastEmit_r - This method is called by target-independent code
147 /// to request that an instruction with the given type, opcode, and
148 /// register operand be emitted.
150 virtual unsigned FastEmit_r(MVT VT,
152 unsigned Opcode, unsigned Op0);
154 /// FastEmit_rr - This method is called by target-independent code
155 /// to request that an instruction with the given type, opcode, and
156 /// register operands be emitted.
158 virtual unsigned FastEmit_rr(MVT VT,
161 unsigned Op0, unsigned Op1);
163 /// FastEmit_ri - This method is called by target-independent code
164 /// to request that an instruction with the given type, opcode, and
165 /// register and immediate operands be emitted.
167 virtual unsigned FastEmit_ri(MVT VT,
170 unsigned Op0, uint64_t Imm);
172 /// FastEmit_rf - This method is called by target-independent code
173 /// to request that an instruction with the given type, opcode, and
174 /// register and floating-point immediate operands be emitted.
176 virtual unsigned FastEmit_rf(MVT VT,
179 unsigned Op0, const ConstantFP *FPImm);
181 /// FastEmit_rri - This method is called by target-independent code
182 /// to request that an instruction with the given type, opcode, and
183 /// register and immediate operands be emitted.
185 virtual unsigned FastEmit_rri(MVT VT,
188 unsigned Op0, unsigned Op1, uint64_t Imm);
190 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
191 /// to emit an instruction with an immediate operand using FastEmit_ri.
192 /// If that fails, it materializes the immediate into a register and try
193 /// FastEmit_rr instead.
194 unsigned FastEmit_ri_(MVT VT,
196 unsigned Op0, uint64_t Imm,
199 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
200 /// to emit an instruction with an immediate operand using FastEmit_rf.
201 /// If that fails, it materializes the immediate into a register and try
202 /// FastEmit_rr instead.
203 unsigned FastEmit_rf_(MVT VT,
205 unsigned Op0, const ConstantFP *FPImm,
208 /// FastEmit_i - This method is called by target-independent code
209 /// to request that an instruction with the given type, opcode, and
210 /// immediate operand be emitted.
211 virtual unsigned FastEmit_i(MVT VT,
216 /// FastEmit_f - This method is called by target-independent code
217 /// to request that an instruction with the given type, opcode, and
218 /// floating-point immediate operand be emitted.
219 virtual unsigned FastEmit_f(MVT VT,
222 const ConstantFP *FPImm);
224 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
225 /// result register in the given register class.
227 unsigned FastEmitInst_(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC);
230 /// FastEmitInst_r - Emit a MachineInstr with one register operand
231 /// and a result register in the given register class.
233 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
234 const TargetRegisterClass *RC,
237 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
238 /// and a result register in the given register class.
240 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
241 const TargetRegisterClass *RC,
242 unsigned Op0, unsigned Op1);
244 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
245 /// and a result register in the given register class.
247 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
248 const TargetRegisterClass *RC,
249 unsigned Op0, uint64_t Imm);
251 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
252 /// and a result register in the given register class.
254 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
255 const TargetRegisterClass *RC,
256 unsigned Op0, const ConstantFP *FPImm);
258 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
259 /// an immediate, and a result register in the given register class.
261 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
262 const TargetRegisterClass *RC,
263 unsigned Op0, unsigned Op1, uint64_t Imm);
265 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
266 /// operand, and a result register in the given register class.
267 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
268 const TargetRegisterClass *RC,
271 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
272 /// from a specified index of a superregister to a specified type.
273 unsigned FastEmitInst_extractsubreg(MVT RetVT,
274 unsigned Op0, uint32_t Idx);
276 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
277 /// with all but the least significant bit set to zero.
278 unsigned FastEmitZExtFromI1(MVT VT,
281 /// FastEmitBranch - Emit an unconditional branch to the given block,
282 /// unless it is the immediate (fall-through) successor, and update
284 void FastEmitBranch(MachineBasicBlock *MBB);
286 unsigned UpdateValueMap(const Value* I, unsigned Reg);
288 unsigned createResultReg(const TargetRegisterClass *RC);
290 /// TargetMaterializeConstant - Emit a constant in a register using
291 /// target-specific logic, such as constant pool loads.
292 virtual unsigned TargetMaterializeConstant(const Constant* C) {
296 /// TargetMaterializeAlloca - Emit an alloca address in a register using
297 /// target-specific logic.
298 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
303 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
305 bool SelectFNeg(const User *I);
307 bool SelectGetElementPtr(const User *I);
309 bool SelectCall(const User *I);
311 bool SelectBitCast(const User *I);
313 bool SelectCast(const User *I, unsigned Opcode);