1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares codegen opcodes and related utilities.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 #define LLVM_CODEGEN_ISDOPCODES_H
19 /// ISD namespace - This namespace contains an enum which represents all of the
20 /// SelectionDAG node types and value types.
24 //===--------------------------------------------------------------------===//
25 /// ISD::NodeType enum - This enum defines the target-independent operators
26 /// for a SelectionDAG.
28 /// Targets may also define target-dependent operator codes for SDNodes. For
29 /// example, on x86, these are the enum values in the X86ISD namespace.
30 /// Targets should aim to use target-independent operators to model their
31 /// instruction sets as much as possible, and only use target-dependent
32 /// operators when they have special requirements.
34 /// Finally, during and after selection proper, SNodes may use special
35 /// operator codes that correspond directly with MachineInstr opcodes. These
36 /// are used to represent selected instructions. See the isMachineOpcode()
37 /// and getMachineOpcode() member functions of SDNode.
40 // DELETED_NODE - This is an illegal value that is used to catch
41 // errors. This opcode is not a legal opcode for any node.
44 // EntryToken - This is the marker used to indicate the start of the region.
47 // TokenFactor - This node takes multiple tokens as input and produces a
48 // single token result. This is used to represent the fact that the operand
49 // operators are independent of each other.
52 // AssertSext, AssertZext - These nodes record if a register contains a
53 // value that has already been zero or sign extended from a narrower type.
54 // These nodes take two operands. The first is the node that has already
55 // been extended, and the second is a value type node indicating the width
57 AssertSext, AssertZext,
59 // Various leaf nodes.
60 BasicBlock, VALUETYPE, CONDCODE, Register,
62 GlobalAddress, GlobalTLSAddress, FrameIndex,
63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
65 // The address of the GOT
68 // FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69 // llvm.returnaddress on the DAG. These nodes take one operand, the index
70 // of the frame or return address to return. An index of zero corresponds
71 // to the current function's frame or return address, an index of one to the
72 // parent's frame or return address, and so on.
73 FRAMEADDR, RETURNADDR,
75 // FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
76 // first (possible) on-stack argument. This is needed for correct stack
77 // adjustment during unwind.
80 // RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the
81 // address of the exception block on entry to an landing pad block.
84 // RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the
85 // address of the Language Specific Data Area for the enclosing function.
88 // RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents
89 // the selection index of the exception thrown.
92 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
93 // 'eh_return' gcc dwarf builtin, which is used to return from
94 // exception. The general meaning is: adjust stack by OFFSET and pass
95 // execution to HANDLER. Many platform-related details also :)
98 // OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
99 // This corresponds to the eh.sjlj.setjmp intrinsic.
100 // It takes an input chain and a pointer to the jump buffer as inputs
101 // and returns an outchain.
104 // OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
105 // This corresponds to the eh.sjlj.longjmp intrinsic.
106 // It takes an input chain and a pointer to the jump buffer as inputs
107 // and returns an outchain.
110 // OUTCHAIN = EH_SJLJ_DISPATCHSETUP(INCHAIN, context)
111 // This corresponds to the eh.sjlj.dispatchsetup intrinsic. It takes an
112 // input chain and a pointer to the sjlj function context as inputs and
113 // returns an outchain. By default, this does nothing. Targets can lower
114 // this to unwind setup code if needed.
115 EH_SJLJ_DISPATCHSETUP,
117 // TargetConstant* - Like Constant*, but the DAG does not do any folding,
118 // simplification, or lowering of the constant. They are used for constants
119 // which are known to fit in the immediate fields of their users, or for
120 // carrying magic numbers which are not values which need to be materialized
125 // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
126 // anything else with this node, and this is valid in the target-specific
127 // dag, turning into a GlobalAddress operand.
129 TargetGlobalTLSAddress,
133 TargetExternalSymbol,
136 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
137 /// This node represents a target intrinsic function with no side effects.
138 /// The first operand is the ID number of the intrinsic from the
139 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
140 /// node returns the result of the intrinsic.
143 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
144 /// This node represents a target intrinsic function with side effects that
145 /// returns a result. The first operand is a chain pointer. The second is
146 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
147 /// operands to the intrinsic follow. The node has two results, the result
148 /// of the intrinsic and an output chain.
151 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
152 /// This node represents a target intrinsic function with side effects that
153 /// does not return a result. The first operand is a chain pointer. The
154 /// second is the ID number of the intrinsic from the llvm::Intrinsic
155 /// namespace. The operands to the intrinsic follow.
158 // CopyToReg - This node has three operands: a chain, a register number to
159 // set to this value, and a value.
162 // CopyFromReg - This node indicates that the input value is a virtual or
163 // physical register that is defined outside of the scope of this
164 // SelectionDAG. The register is available from the RegisterSDNode object.
167 // UNDEF - An undefined node
170 // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
171 // a Constant, which is required to be operand #1) half of the integer or
172 // float value specified as operand #0. This is only for use before
173 // legalization, for values that will be broken into multiple registers.
176 // BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given
177 // two values of the same integer value type, this produces a value twice as
178 // big. Like EXTRACT_ELEMENT, this can only be used before legalization.
181 // MERGE_VALUES - This node takes multiple discrete operands and returns
182 // them all as its individual results. This nodes has exactly the same
183 // number of inputs and outputs. This node is useful for some pieces of the
184 // code generator that want to think about a single node with multiple
185 // results, not multiple nodes.
188 // Simple integer binary arithmetic operators.
189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
191 // SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
192 // a signed/unsigned value of type i[2*N], and return the full value as
193 // two results, each of type iN.
194 SMUL_LOHI, UMUL_LOHI,
196 // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
200 // CARRY_FALSE - This node is used when folding other nodes,
201 // like ADDC/SUBC, which indicate the carry result is always false.
204 // Carry-setting nodes for multiple precision addition and subtraction.
205 // These nodes take two operands of the same value type, and produce two
206 // results. The first result is the normal add or sub result, the second
207 // result is the carry flag result.
210 // Carry-using nodes for multiple precision addition and subtraction. These
211 // nodes take three operands: The first two are the normal lhs and rhs to
212 // the add or sub, and the third is the input carry flag. These nodes
213 // produce two results; the normal result of the add or sub, and the output
214 // carry flag. These nodes both read and write a carry flag to allow them
215 // to them to be chained together for add and sub of arbitrarily large
219 // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
220 // These nodes take two operands: the normal LHS and RHS to the add. They
221 // produce two results: the normal result of the add, and a boolean that
222 // indicates if an overflow occured (*not* a flag, because it may be stored
223 // to memory, etc.). If the type of the boolean is not i1 then the high
224 // bits conform to getBooleanContents.
225 // These nodes are generated from the llvm.[su]add.with.overflow intrinsics.
228 // Same for subtraction
231 // Same for multiplication
234 // Simple binary floating point operators.
235 FADD, FSUB, FMUL, FDIV, FREM,
237 // FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
238 // DAG node does not require that X and Y have the same type, just that they
239 // are both floating point. X and the result must have the same type.
240 // FCOPYSIGN(f32, f64) is allowed.
243 // INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
244 // value as an integer 0/1 value.
247 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
248 /// specified, possibly variable, elements. The number of elements is
249 /// required to be a power of two. The types of the operands must all be
250 /// the same and must match the vector element type, except that integer
251 /// types are allowed to be larger than the element type, in which case
252 /// the operands are implicitly truncated.
255 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
256 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
257 /// element type then VAL is truncated before replacement.
260 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
261 /// identified by the (potentially variable) element number IDX. If the
262 /// return type is an integer type larger than the element type of the
263 /// vector, the result is extended to the width of the return type.
266 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
267 /// vector type with the same length and element type, this produces a
268 /// concatenated vector result value, with length equal to the sum of the
269 /// lengths of the input vectors.
272 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
273 /// with VECTOR2 inserted into VECTOR1 at the (potentially
274 /// variable) element number IDX, which must be a multiple of the
275 /// VECTOR2 vector length. The elements of VECTOR1 starting at
276 /// IDX are overwritten with VECTOR2. Elements IDX through
277 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
280 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
281 /// vector value) starting with the element number IDX, which must be a
282 /// constant multiple of the result vector length.
285 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
286 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
287 /// values that indicate which value (or undef) each result element will
288 /// get. These constant ints are accessible through the
289 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
290 /// 'vperm' instruction, except that the indices must be constants and are
291 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
294 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
295 /// scalar value into element 0 of the resultant vector type. The top
296 /// elements 1 to N-1 of the N-element vector are undefined. The type
297 /// of the operand must match the vector element type, except when they
298 /// are integer types. In this case the operand is allowed to be wider
299 /// than the vector element type, and is implicitly truncated to it.
302 // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
303 // an unsigned/signed value of type i[2*N], then return the top part.
306 /// Bitwise operators - logical and, logical or, logical xor.
309 /// Shift and rotation operations. After legalization, the type of the
310 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
311 /// the shift amount can be any type, but care must be taken to ensure it is
312 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
313 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
314 /// to represent the shift amount. By convention, DAGCombine and
315 /// SelectionDAGBuilder forces these shift amounts to i32 for simplicity.
317 SHL, SRA, SRL, ROTL, ROTR,
319 /// Byte Swap and Counting operators.
320 BSWAP, CTTZ, CTLZ, CTPOP,
322 // Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
323 // i1 then the high bits must conform to getBooleanContents.
326 // Select with condition operator - This selects between a true value and
327 // a false value (ops #2 and #3) based on the boolean result of comparing
328 // the lhs and rhs (ops #0 and #1) of a conditional expression with the
329 // condition code in op #4, a CondCodeSDNode.
332 // SetCC operator - This evaluates to a true value iff the condition is
333 // true. If the result value type is not i1 then the high bits conform
334 // to getBooleanContents. The operands to this are the left and right
335 // operands to compare (ops #0, and #1) and the condition code to compare
336 // them with (op #2) as a CondCodeSDNode.
339 // RESULT = VSETCC(LHS, RHS, COND) operator - This evaluates to a vector of
340 // integer elements with all bits of the result elements set to true if the
341 // comparison is true or all cleared if the comparison is false. The
342 // operands to this are the left and right operands to compare (LHS/RHS) and
343 // the condition code to compare them with (COND) as a CondCodeSDNode.
346 // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
347 // integer shift operations, just like ADD/SUB_PARTS. The operation
349 // [Lo,Hi] = op [LoLHS,HiLHS], Amt
350 SHL_PARTS, SRA_PARTS, SRL_PARTS,
352 // Conversion operators. These are all single input single output
353 // operations. For all of these, the result type must be strictly
354 // wider or narrower (depending on the operation) than the source
357 // SIGN_EXTEND - Used for integer types, replicating the sign bit
361 // ZERO_EXTEND - Used for integer types, zeroing the new bits.
364 // ANY_EXTEND - Used for integer types. The high bits are undefined.
367 // TRUNCATE - Completely drop the high bits.
370 // [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
371 // depends on the first letter) to floating point.
375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
376 // sign extend a small value in a large integer register (e.g. sign
377 // extending the low 8 bits of a 32-bit register to fill the top 24 bits
378 // with the 7th bit). The size of the smaller type is indicated by the 1th
379 // operand, a ValueType node.
382 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
387 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
388 /// down to the precision of the destination VT. TRUNC is a flag, which is
389 /// always an integer that is zero or one. If TRUNC is 0, this is a
390 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
393 /// The TRUNC = 1 case is used in cases where we know that the value will
394 /// not be modified by the node, because Y is not using any of the extra
395 /// precision of source type. This allows certain transformations like
396 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
397 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
400 // FLT_ROUNDS_ - Returns current rounding mode:
403 // 1 Round to nearest
408 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
409 /// rounds it to a floating point value. It then promotes it and returns it
410 /// in a register of the same size. This operation effectively just
411 /// discards excess precision. The type to round down to is specified by
412 /// the VT operand, a VTSDNode.
415 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
418 // BITCAST - This operator converts between integer, vector and FP
419 // values, as if the value was stored to memory with one type and loaded
420 // from the same address with the other type (or equivalently for vector
421 // format conversions, etc). The source and result are required to have
422 // the same bit size (e.g. f32 <-> i32). This can also be used for
423 // int-to-int or fp-to-fp conversions, but that is a noop, deleted by
427 // CONVERT_RNDSAT - This operator is used to support various conversions
428 // between various types (float, signed, unsigned and vectors of those
429 // types) with rounding and saturation. NOTE: Avoid using this operator as
430 // most target don't support it and the operator might be removed in the
431 // future. It takes the following arguments:
433 // 1) dest type (type to convert to)
434 // 2) src type (type to convert from)
437 // 5) ISD::CvtCode indicating the type of conversion to do
440 // FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
441 // promotions and truncation for half-precision (16 bit) floating
442 // numbers. We need special nodes since FP16 is a storage-only type with
443 // special semantics of operations.
444 FP16_TO_FP32, FP32_TO_FP16,
446 // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
447 // FLOG, FLOG2, FLOG10, FEXP, FEXP2,
448 // FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating
449 // point operations. These are inspired by libm.
450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
451 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
454 // LOAD and STORE have token chains as their first operand, then the same
455 // operands as an LLVM load/store instruction, then an offset node that
456 // is added / subtracted from the base pointer to form the address (for
457 // indexed memory ops).
460 // DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
461 // to a specified boundary. This node always has two return values: a new
462 // stack pointer value and a chain. The first operand is the token chain,
463 // the second is the number of bytes to allocate, and the third is the
464 // alignment boundary. The size is guaranteed to be a multiple of the stack
465 // alignment, and the alignment is guaranteed to be bigger than the stack
466 // alignment (if required) or 0 to get standard stack alignment.
469 // Control flow instructions. These all have token chains.
471 // BR - Unconditional branch. The first operand is the chain
472 // operand, the second is the MBB to branch to.
475 // BRIND - Indirect branch. The first operand is the chain, the second
476 // is the value to branch to, which must be of the same type as the target's
480 // BR_JT - Jumptable branch. The first operand is the chain, the second
481 // is the jumptable index, the last one is the jumptable entry index.
484 // BRCOND - Conditional branch. The first operand is the chain, the
485 // second is the condition, the third is the block to branch to if the
486 // condition is true. If the type of the condition is not i1, then the
487 // high bits must conform to getBooleanContents.
490 // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
491 // that the condition is represented as condition code, and two nodes to
492 // compare, rather than as a combined SetCC node. The operands in order are
493 // chain, cc, lhs, rhs, block to branch to if condition is true.
496 // INLINEASM - Represents an inline asm block. This node always has two
497 // return values: a chain and a flag result. The inputs are as follows:
498 // Operand #0 : Input chain.
499 // Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
500 // Operand #2 : a MDNodeSDNode with the !srcloc metadata.
501 // Operand #3 : HasSideEffect, IsAlignStack bits.
502 // After this, it is followed by a list of operands with this format:
503 // ConstantSDNode: Flags that encode whether it is a mem or not, the
504 // of operands that follow, etc. See InlineAsm.h.
505 // ... however many operands ...
506 // Operand #last: Optional, an incoming flag.
508 // The variable width operands are required to represent target addressing
509 // modes as a single "operand", even though they may have multiple
513 // EH_LABEL - Represents a label in mid basic block used to track
514 // locations needed for debug and exception handling tables. These nodes
515 // take a chain as input and return a chain.
518 // STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
519 // value, the same type as the pointer type for the system, and an output
523 // STACKRESTORE has two operands, an input chain and a pointer to restore to
524 // it returns an output chain.
527 // CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of
528 // a call sequence, and carry arbitrary information that target might want
529 // to know. The first operand is a chain, the rest are specified by the
530 // target and not touched by the DAG optimizers.
531 // CALLSEQ_START..CALLSEQ_END pairs may not be nested.
532 CALLSEQ_START, // Beginning of a call sequence
533 CALLSEQ_END, // End of a call sequence
535 // VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
536 // and the alignment. It returns a pair of values: the vaarg value and a
540 // VACOPY - VACOPY has five operands: an input chain, a destination pointer,
541 // a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
545 // VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a
546 // pointer, and a SRCVALUE.
549 // SRCVALUE - This is a node type that holds a Value* that is used to
550 // make reference to a value in the LLVM IR.
553 // MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
554 // reference metadata in the IR.
557 // PCMARKER - This corresponds to the pcmarker intrinsic.
560 // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
561 // The only operand is a chain and a value and a chain are produced. The
562 // value is the contents of the architecture specific cycle counter like
563 // register (or other high accuracy low latency clock source)
566 // HANDLENODE node - Used as a handle for various purposes.
569 // TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
570 // It takes as input a token chain, the pointer to the trampoline,
571 // the pointer to the nested function, the pointer to pass for the
572 // 'nest' parameter, a SRCVALUE for the trampoline and another for
573 // the nested function (allowing targets to access the original
574 // Function*). It produces the result of the intrinsic and a token
578 // TRAP - Trapping instruction
581 // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
582 // their first operand. The other operands are the address to prefetch,
583 // read / write specifier, and locality specifier.
586 // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
587 // store-store, device)
588 // This corresponds to the memory.barrier intrinsic.
589 // it takes an input chain, 4 operands to specify the type of barrier, an
590 // operand specifying if the barrier applies to device and uncached memory
591 // and produces an output chain.
594 // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
595 // this corresponds to the atomic.lcs intrinsic.
596 // cmp is compared to *ptr, and if equal, swap is stored in *ptr.
597 // the return is always the original value in *ptr
600 // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
601 // this corresponds to the atomic.swap intrinsic.
602 // amt is stored to *ptr atomically.
603 // the return is always the original value in *ptr
606 // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
607 // this corresponds to the atomic.load.[OpName] intrinsic.
608 // op(*ptr, amt) is stored to *ptr atomically.
609 // the return is always the original value in *ptr
621 /// BUILTIN_OP_END - This must be the last enum value in this list.
622 /// The target-specific pre-isel opcode values start here.
626 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
627 /// which do not reference a specific memory location should be less than
628 /// this value. Those that do must not be less than this value, and can
629 /// be used with SelectionDAG::getMemIntrinsicNode.
630 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150;
632 //===--------------------------------------------------------------------===//
633 /// MemIndexedMode enum - This enum defines the load / store indexed
634 /// addressing modes.
636 /// UNINDEXED "Normal" load / store. The effective address is already
637 /// computed and is available in the base pointer. The offset
638 /// operand is always undefined. In addition to producing a
639 /// chain, an unindexed load produces one value (result of the
640 /// load); an unindexed store does not produce a value.
642 /// PRE_INC Similar to the unindexed mode where the effective address is
643 /// PRE_DEC the value of the base pointer add / subtract the offset.
644 /// It considers the computation as being folded into the load /
645 /// store operation (i.e. the load / store does the address
646 /// computation as well as performing the memory transaction).
647 /// The base operand is always undefined. In addition to
648 /// producing a chain, pre-indexed load produces two values
649 /// (result of the load and the result of the address
650 /// computation); a pre-indexed store produces one value (result
651 /// of the address computation).
653 /// POST_INC The effective address is the value of the base pointer. The
654 /// POST_DEC value of the offset operand is then added to / subtracted
655 /// from the base after memory transaction. In addition to
656 /// producing a chain, post-indexed load produces two values
657 /// (the result of the load and the result of the base +/- offset
658 /// computation); a post-indexed store produces one value (the
659 /// the result of the base +/- offset computation).
660 enum MemIndexedMode {
669 //===--------------------------------------------------------------------===//
670 /// LoadExtType enum - This enum defines the three variants of LOADEXT
671 /// (load with extension).
673 /// SEXTLOAD loads the integer operand and sign extends it to a larger
674 /// integer result type.
675 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
676 /// integer result type.
677 /// EXTLOAD is used for two things: floating point extending loads and
678 /// integer extending loads [the top bits are undefined].
687 //===--------------------------------------------------------------------===//
688 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
689 /// below work out, when considering SETFALSE (something that never exists
690 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
691 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
692 /// to. If the "N" column is 1, the result of the comparison is undefined if
693 /// the input is a NAN.
695 /// All of these (except for the 'always folded ops') should be handled for
696 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
697 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
699 /// Note that these are laid out in a specific order to allow bit-twiddling
700 /// to transform conditions.
702 // Opcode N U L G E Intuitive operation
703 SETFALSE, // 0 0 0 0 Always false (always folded)
704 SETOEQ, // 0 0 0 1 True if ordered and equal
705 SETOGT, // 0 0 1 0 True if ordered and greater than
706 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
707 SETOLT, // 0 1 0 0 True if ordered and less than
708 SETOLE, // 0 1 0 1 True if ordered and less than or equal
709 SETONE, // 0 1 1 0 True if ordered and operands are unequal
710 SETO, // 0 1 1 1 True if ordered (no nans)
711 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
712 SETUEQ, // 1 0 0 1 True if unordered or equal
713 SETUGT, // 1 0 1 0 True if unordered or greater than
714 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
715 SETULT, // 1 1 0 0 True if unordered or less than
716 SETULE, // 1 1 0 1 True if unordered, less than, or equal
717 SETUNE, // 1 1 1 0 True if unordered or not equal
718 SETTRUE, // 1 1 1 1 Always true (always folded)
719 // Don't care operations: undefined if the input is a nan.
720 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
721 SETEQ, // 1 X 0 0 1 True if equal
722 SETGT, // 1 X 0 1 0 True if greater than
723 SETGE, // 1 X 0 1 1 True if greater than or equal
724 SETLT, // 1 X 1 0 0 True if less than
725 SETLE, // 1 X 1 0 1 True if less than or equal
726 SETNE, // 1 X 1 1 0 True if not equal
727 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
729 SETCC_INVALID // Marker value.
732 /// isSignedIntSetCC - Return true if this is a setcc instruction that
733 /// performs a signed comparison when used with integer operands.
734 inline bool isSignedIntSetCC(CondCode Code) {
735 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
738 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that
739 /// performs an unsigned comparison when used with integer operands.
740 inline bool isUnsignedIntSetCC(CondCode Code) {
741 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
744 /// isTrueWhenEqual - Return true if the specified condition returns true if
745 /// the two operands to the condition are equal. Note that if one of the two
746 /// operands is a NaN, this value is meaningless.
747 inline bool isTrueWhenEqual(CondCode Cond) {
748 return ((int)Cond & 1) != 0;
751 /// getUnorderedFlavor - This function returns 0 if the condition is always
752 /// false if an operand is a NaN, 1 if the condition is always true if the
753 /// operand is a NaN, and 2 if the condition is undefined if the operand is a
755 inline unsigned getUnorderedFlavor(CondCode Cond) {
756 return ((int)Cond >> 3) & 3;
759 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
760 /// 'op' is a valid SetCC operation.
761 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
763 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
764 /// when given the operation for (X op Y).
765 CondCode getSetCCSwappedOperands(CondCode Operation);
767 /// getSetCCOrOperation - Return the result of a logical OR between different
768 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This
769 /// function returns SETCC_INVALID if it is not possible to represent the
770 /// resultant comparison.
771 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
773 /// getSetCCAndOperation - Return the result of a logical AND between
774 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
775 /// function returns SETCC_INVALID if it is not possible to represent the
776 /// resultant comparison.
777 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
779 //===--------------------------------------------------------------------===//
780 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
783 CVT_FF, // Float from Float
784 CVT_FS, // Float from Signed
785 CVT_FU, // Float from Unsigned
786 CVT_SF, // Signed from Float
787 CVT_UF, // Unsigned from Float
788 CVT_SS, // Signed from Signed
789 CVT_SU, // Signed from Unsigned
790 CVT_US, // Unsigned from Signed
791 CVT_UU, // Unsigned from Unsigned
792 CVT_INVALID // Marker - Invalid opcode
795 } // end llvm::ISD namespace
797 } // end llvm namespace