1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares codegen opcodes and related utilities.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 #define LLVM_CODEGEN_ISDOPCODES_H
19 /// ISD namespace - This namespace contains an enum which represents all of the
20 /// SelectionDAG node types and value types.
24 //===--------------------------------------------------------------------===//
25 /// ISD::NodeType enum - This enum defines the target-independent operators
26 /// for a SelectionDAG.
28 /// Targets may also define target-dependent operator codes for SDNodes. For
29 /// example, on x86, these are the enum values in the X86ISD namespace.
30 /// Targets should aim to use target-independent operators to model their
31 /// instruction sets as much as possible, and only use target-dependent
32 /// operators when they have special requirements.
34 /// Finally, during and after selection proper, SNodes may use special
35 /// operator codes that correspond directly with MachineInstr opcodes. These
36 /// are used to represent selected instructions. See the isMachineOpcode()
37 /// and getMachineOpcode() member functions of SDNode.
40 /// DELETED_NODE - This is an illegal value that is used to catch
41 /// errors. This opcode is not a legal opcode for any node.
44 /// EntryToken - This is the marker used to indicate the start of a region.
47 /// TokenFactor - This node takes multiple tokens as input and produces a
48 /// single token result. This is used to represent the fact that the operand
49 /// operators are independent of each other.
52 /// AssertSext, AssertZext - These nodes record if a register contains a
53 /// value that has already been zero or sign extended from a narrower type.
54 /// These nodes take two operands. The first is the node that has already
55 /// been extended, and the second is a value type node indicating the width
57 AssertSext, AssertZext,
59 /// Various leaf nodes.
60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
62 GlobalAddress, GlobalTLSAddress, FrameIndex,
63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
65 /// The address of the GOT
68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
70 /// of the frame or return address to return. An index of zero corresponds
71 /// to the current function's frame or return address, an index of one to
72 /// the parent's frame or return address, and so on.
73 FRAMEADDR, RETURNADDR,
75 /// FRAME_ALLOC_RECOVER - Represents the llvm.framerecover
76 /// intrinsic. Materializes the offset from the frame pointer of another
77 /// function to the result of llvm.frameallocate.
80 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
81 /// the DAG, which implements the named register global variables extension.
85 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
86 /// first (possible) on-stack argument. This is needed for correct stack
87 /// adjustment during unwind.
90 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
91 /// 'eh_return' gcc dwarf builtin, which is used to return from
92 /// exception. The general meaning is: adjust stack by OFFSET and pass
93 /// execution to HANDLER. Many platform-related details also :)
96 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
97 /// This corresponds to the eh.sjlj.setjmp intrinsic.
98 /// It takes an input chain and a pointer to the jump buffer as inputs
99 /// and returns an outchain.
102 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
103 /// This corresponds to the eh.sjlj.longjmp intrinsic.
104 /// It takes an input chain and a pointer to the jump buffer as inputs
105 /// and returns an outchain.
108 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
109 /// simplification, or lowering of the constant. They are used for constants
110 /// which are known to fit in the immediate fields of their users, or for
111 /// carrying magic numbers which are not values which need to be
112 /// materialized in registers.
116 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
117 /// anything else with this node, and this is valid in the target-specific
118 /// dag, turning into a GlobalAddress operand.
120 TargetGlobalTLSAddress,
124 TargetExternalSymbol,
129 /// TargetIndex - Like a constant pool entry, but with completely
130 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
131 /// 64-bit index. Targets can use this however they like.
134 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
135 /// This node represents a target intrinsic function with no side effects.
136 /// The first operand is the ID number of the intrinsic from the
137 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
138 /// node returns the result of the intrinsic.
141 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
142 /// This node represents a target intrinsic function with side effects that
143 /// returns a result. The first operand is a chain pointer. The second is
144 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
145 /// operands to the intrinsic follow. The node has two results, the result
146 /// of the intrinsic and an output chain.
149 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
150 /// This node represents a target intrinsic function with side effects that
151 /// does not return a result. The first operand is a chain pointer. The
152 /// second is the ID number of the intrinsic from the llvm::Intrinsic
153 /// namespace. The operands to the intrinsic follow.
156 /// CopyToReg - This node has three operands: a chain, a register number to
157 /// set to this value, and a value.
160 /// CopyFromReg - This node indicates that the input value is a virtual or
161 /// physical register that is defined outside of the scope of this
162 /// SelectionDAG. The register is available from the RegisterSDNode object.
165 /// UNDEF - An undefined node.
168 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
169 /// a Constant, which is required to be operand #1) half of the integer or
170 /// float value specified as operand #0. This is only for use before
171 /// legalization, for values that will be broken into multiple registers.
174 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
175 /// Given two values of the same integer value type, this produces a value
176 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
180 /// MERGE_VALUES - This node takes multiple discrete operands and returns
181 /// them all as its individual results. This nodes has exactly the same
182 /// number of inputs and outputs. This node is useful for some pieces of the
183 /// code generator that want to think about a single node with multiple
184 /// results, not multiple nodes.
187 /// Simple integer binary arithmetic operators.
188 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
190 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
191 /// a signed/unsigned value of type i[2*N], and return the full value as
192 /// two results, each of type iN.
193 SMUL_LOHI, UMUL_LOHI,
195 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
196 /// remainder result.
199 /// CARRY_FALSE - This node is used when folding other nodes,
200 /// like ADDC/SUBC, which indicate the carry result is always false.
203 /// Carry-setting nodes for multiple precision addition and subtraction.
204 /// These nodes take two operands of the same value type, and produce two
205 /// results. The first result is the normal add or sub result, the second
206 /// result is the carry flag result.
209 /// Carry-using nodes for multiple precision addition and subtraction. These
210 /// nodes take three operands: The first two are the normal lhs and rhs to
211 /// the add or sub, and the third is the input carry flag. These nodes
212 /// produce two results; the normal result of the add or sub, and the output
213 /// carry flag. These nodes both read and write a carry flag to allow them
214 /// to them to be chained together for add and sub of arbitrarily large
218 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
219 /// These nodes take two operands: the normal LHS and RHS to the add. They
220 /// produce two results: the normal result of the add, and a boolean that
221 /// indicates if an overflow occurred (*not* a flag, because it may be store
222 /// to memory, etc.). If the type of the boolean is not i1 then the high
223 /// bits conform to getBooleanContents.
224 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
227 /// Same for subtraction.
230 /// Same for multiplication.
233 /// Simple binary floating point operators.
234 FADD, FSUB, FMUL, FDIV, FREM,
236 /// FMA - Perform a * b + c with no intermediate rounding step.
239 /// FMAD - Perform a * b + c, while getting the same result as the
240 /// separately rounded operations.
243 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
244 /// DAG node does not require that X and Y have the same type, just that
245 /// they are both floating point. X and the result must have the same type.
246 /// FCOPYSIGN(f32, f64) is allowed.
249 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
250 /// value as an integer 0/1 value.
253 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
254 /// specified, possibly variable, elements. The number of elements is
255 /// required to be a power of two. The types of the operands must all be
256 /// the same and must match the vector element type, except that integer
257 /// types are allowed to be larger than the element type, in which case
258 /// the operands are implicitly truncated.
261 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
262 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
263 /// element type then VAL is truncated before replacement.
266 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
267 /// identified by the (potentially variable) element number IDX. If the
268 /// return type is an integer type larger than the element type of the
269 /// vector, the result is extended to the width of the return type.
272 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
273 /// vector type with the same length and element type, this produces a
274 /// concatenated vector result value, with length equal to the sum of the
275 /// lengths of the input vectors.
278 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
279 /// with VECTOR2 inserted into VECTOR1 at the (potentially
280 /// variable) element number IDX, which must be a multiple of the
281 /// VECTOR2 vector length. The elements of VECTOR1 starting at
282 /// IDX are overwritten with VECTOR2. Elements IDX through
283 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
286 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
287 /// vector value) starting with the element number IDX, which must be a
288 /// constant multiple of the result vector length.
291 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
292 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
293 /// values that indicate which value (or undef) each result element will
294 /// get. These constant ints are accessible through the
295 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
296 /// 'vperm' instruction, except that the indices must be constants and are
297 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
300 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
301 /// scalar value into element 0 of the resultant vector type. The top
302 /// elements 1 to N-1 of the N-element vector are undefined. The type
303 /// of the operand must match the vector element type, except when they
304 /// are integer types. In this case the operand is allowed to be wider
305 /// than the vector element type, and is implicitly truncated to it.
308 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
309 /// producing an unsigned/signed value of type i[2*N], then return the top
313 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
315 SMIN, SMAX, UMIN, UMAX,
317 /// Bitwise operators - logical and, logical or, logical xor.
320 /// Shift and rotation operations. After legalization, the type of the
321 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
322 /// the shift amount can be any type, but care must be taken to ensure it is
323 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
324 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
325 /// to represent the shift amount.
326 /// When the 1st operand is a vector, the shift amount must be in the same
327 /// type. (TLI.getShiftAmountTy() will return the same type when the input
328 /// type is a vector.)
329 SHL, SRA, SRL, ROTL, ROTR,
331 /// Byte Swap and Counting operators.
332 BSWAP, CTTZ, CTLZ, CTPOP,
334 /// Bit counting operators with an undefined result for zero inputs.
335 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
337 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
338 /// i1 then the high bits must conform to getBooleanContents.
341 /// Select with a vector condition (op #0) and two vector operands (ops #1
342 /// and #2), returning a vector result. All vectors have the same length.
343 /// Much like the scalar select and setcc, each bit in the condition selects
344 /// whether the corresponding result element is taken from op #1 or op #2.
345 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
346 /// change the condition type in order to match the VSELECT node using a
347 /// pattern. The condition follows the BooleanContent format of the target.
350 /// Select with condition operator - This selects between a true value and
351 /// a false value (ops #2 and #3) based on the boolean result of comparing
352 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
353 /// condition code in op #4, a CondCodeSDNode.
356 /// SetCC operator - This evaluates to a true value iff the condition is
357 /// true. If the result value type is not i1 then the high bits conform
358 /// to getBooleanContents. The operands to this are the left and right
359 /// operands to compare (ops #0, and #1) and the condition code to compare
360 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
361 /// then the result type must also be a vector type.
364 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
365 /// integer shift operations, just like ADD/SUB_PARTS. The operation
367 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
368 SHL_PARTS, SRA_PARTS, SRL_PARTS,
370 /// Conversion operators. These are all single input single output
371 /// operations. For all of these, the result type must be strictly
372 /// wider or narrower (depending on the operation) than the source
375 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
379 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
382 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
385 /// TRUNCATE - Completely drop the high bits.
388 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
389 /// depends on the first letter) to floating point.
393 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
394 /// sign extend a small value in a large integer register (e.g. sign
395 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
396 /// with the 7th bit). The size of the smaller type is indicated by the 1th
397 /// operand, a ValueType node.
400 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
401 /// in-register any-extension of the low lanes of an integer vector. The
402 /// result type must have fewer elements than the operand type, and those
403 /// elements must be larger integer types such that the total size of the
404 /// operand type and the result type match. Each of the low operand
405 /// elements is any-extended into the corresponding, wider result
406 /// elements with the high bits becoming undef.
407 ANY_EXTEND_VECTOR_INREG,
409 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
410 /// in-register sign-extension of the low lanes of an integer vector. The
411 /// result type must have fewer elements than the operand type, and those
412 /// elements must be larger integer types such that the total size of the
413 /// operand type and the result type match. Each of the low operand
414 /// elements is sign-extended into the corresponding, wider result
416 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
417 // scalars, but it also doesn't handle vectors well. Either it should be
418 // restricted to scalars or this node (and its handling) should be merged
420 SIGN_EXTEND_VECTOR_INREG,
422 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
423 /// in-register zero-extension of the low lanes of an integer vector. The
424 /// result type must have fewer elements than the operand type, and those
425 /// elements must be larger integer types such that the total size of the
426 /// operand type and the result type match. Each of the low operand
427 /// elements is zero-extended into the corresponding, wider result
429 ZERO_EXTEND_VECTOR_INREG,
431 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
436 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
437 /// down to the precision of the destination VT. TRUNC is a flag, which is
438 /// always an integer that is zero or one. If TRUNC is 0, this is a
439 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
442 /// The TRUNC = 1 case is used in cases where we know that the value will
443 /// not be modified by the node, because Y is not using any of the extra
444 /// precision of source type. This allows certain transformations like
445 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
446 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
449 /// FLT_ROUNDS_ - Returns current rounding mode:
452 /// 1 Round to nearest
457 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
458 /// rounds it to a floating point value. It then promotes it and returns it
459 /// in a register of the same size. This operation effectively just
460 /// discards excess precision. The type to round down to is specified by
461 /// the VT operand, a VTSDNode.
464 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
467 /// BITCAST - This operator converts between integer, vector and FP
468 /// values, as if the value was stored to memory with one type and loaded
469 /// from the same address with the other type (or equivalently for vector
470 /// format conversions, etc). The source and result are required to have
471 /// the same bit size (e.g. f32 <-> i32). This can also be used for
472 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
476 /// ADDRSPACECAST - This operator converts between pointers of different
480 /// CONVERT_RNDSAT - This operator is used to support various conversions
481 /// between various types (float, signed, unsigned and vectors of those
482 /// types) with rounding and saturation. NOTE: Avoid using this operator as
483 /// most target don't support it and the operator might be removed in the
484 /// future. It takes the following arguments:
486 /// 1) dest type (type to convert to)
487 /// 2) src type (type to convert from)
489 /// 4) saturation imm
490 /// 5) ISD::CvtCode indicating the type of conversion to do
493 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
494 /// and truncation for half-precision (16 bit) floating numbers. These nodes
495 /// form a semi-softened interface for dealing with f16 (as an i16), which
496 /// is often a storage-only type but has native conversions.
497 FP16_TO_FP, FP_TO_FP16,
499 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
500 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
501 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
502 /// floating point operations. These are inspired by libm.
503 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
504 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
505 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
508 /// FSINCOS - Compute both fsin and fcos as a single operation.
511 /// LOAD and STORE have token chains as their first operand, then the same
512 /// operands as an LLVM load/store instruction, then an offset node that
513 /// is added / subtracted from the base pointer to form the address (for
514 /// indexed memory ops).
517 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
518 /// to a specified boundary. This node always has two return values: a new
519 /// stack pointer value and a chain. The first operand is the token chain,
520 /// the second is the number of bytes to allocate, and the third is the
521 /// alignment boundary. The size is guaranteed to be a multiple of the
522 /// stack alignment, and the alignment is guaranteed to be bigger than the
523 /// stack alignment (if required) or 0 to get standard stack alignment.
526 /// Control flow instructions. These all have token chains.
528 /// BR - Unconditional branch. The first operand is the chain
529 /// operand, the second is the MBB to branch to.
532 /// BRIND - Indirect branch. The first operand is the chain, the second
533 /// is the value to branch to, which must be of the same type as the
534 /// target's pointer type.
537 /// BR_JT - Jumptable branch. The first operand is the chain, the second
538 /// is the jumptable index, the last one is the jumptable entry index.
541 /// BRCOND - Conditional branch. The first operand is the chain, the
542 /// second is the condition, the third is the block to branch to if the
543 /// condition is true. If the type of the condition is not i1, then the
544 /// high bits must conform to getBooleanContents.
547 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
548 /// that the condition is represented as condition code, and two nodes to
549 /// compare, rather than as a combined SetCC node. The operands in order
550 /// are chain, cc, lhs, rhs, block to branch to if condition is true.
553 /// INLINEASM - Represents an inline asm block. This node always has two
554 /// return values: a chain and a flag result. The inputs are as follows:
555 /// Operand #0 : Input chain.
556 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
557 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
558 /// Operand #3 : HasSideEffect, IsAlignStack bits.
559 /// After this, it is followed by a list of operands with this format:
560 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
561 /// of operands that follow, etc. See InlineAsm.h.
562 /// ... however many operands ...
563 /// Operand #last: Optional, an incoming flag.
565 /// The variable width operands are required to represent target addressing
566 /// modes as a single "operand", even though they may have multiple
570 /// EH_LABEL - Represents a label in mid basic block used to track
571 /// locations needed for debug and exception handling tables. These nodes
572 /// take a chain as input and return a chain.
575 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
576 /// value, the same type as the pointer type for the system, and an output
580 /// STACKRESTORE has two operands, an input chain and a pointer to restore
581 /// to it returns an output chain.
584 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
585 /// of a call sequence, and carry arbitrary information that target might
586 /// want to know. The first operand is a chain, the rest are specified by
587 /// the target and not touched by the DAG optimizers.
588 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
589 CALLSEQ_START, // Beginning of a call sequence
590 CALLSEQ_END, // End of a call sequence
592 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
593 /// and the alignment. It returns a pair of values: the vaarg value and a
597 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
598 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
602 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
603 /// pointer, and a SRCVALUE.
606 /// SRCVALUE - This is a node type that holds a Value* that is used to
607 /// make reference to a value in the LLVM IR.
610 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
611 /// reference metadata in the IR.
614 /// PCMARKER - This corresponds to the pcmarker intrinsic.
617 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
618 /// The only operand is a chain and a value and a chain are produced. The
619 /// value is the contents of the architecture specific cycle counter like
620 /// register (or other high accuracy low latency clock source)
623 /// HANDLENODE node - Used as a handle for various purposes.
626 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
627 /// takes as input a token chain, the pointer to the trampoline, the pointer
628 /// to the nested function, the pointer to pass for the 'nest' parameter, a
629 /// SRCVALUE for the trampoline and another for the nested function
630 /// (allowing targets to access the original Function*).
631 /// It produces a token chain as output.
634 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
635 /// It takes a pointer to the trampoline and produces a (possibly) new
636 /// pointer to the same trampoline with platform-specific adjustments
637 /// applied. The pointer it returns points to an executable block of code.
640 /// TRAP - Trapping instruction
643 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
646 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
647 /// is the chain. The other operands are the address to prefetch,
648 /// read / write specifier, locality specifier and instruction / data cache
652 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
653 /// This corresponds to the fence instruction. It takes an input chain, and
654 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
657 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
658 /// This corresponds to "load atomic" instruction.
661 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
662 /// This corresponds to "store atomic" instruction.
665 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
666 /// For double-word atomic operations:
667 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
669 /// This corresponds to the cmpxchg instruction.
672 /// Val, Success, OUTCHAIN
673 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
674 /// N.b. this is still a strong cmpxchg operation, so
675 /// Success == "Val == cmp".
676 ATOMIC_CMP_SWAP_WITH_SUCCESS,
678 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
679 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
680 /// For double-word atomic operations:
681 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
682 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
683 /// These correspond to the atomicrmw instruction.
696 // Masked load and store - consecutive vector load and store operations
697 // with additional mask operand that prevents memory accesses to the
701 // Masked gather and scatter - load and store operations for a vector of
702 // random addresses with additional mask operand that prevents memory
703 // accesses to the masked-off lanes.
706 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
707 /// is the chain and the second operand is the alloca pointer.
708 LIFETIME_START, LIFETIME_END,
710 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
711 /// beginning and end of GC transition sequence, and carry arbitrary
712 /// information that target might need for lowering. The first operand is
713 /// a chain, the rest are specified by the target and not touched by the DAG
714 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
719 /// BUILTIN_OP_END - This must be the last enum value in this list.
720 /// The target-specific pre-isel opcode values start here.
724 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
725 /// which do not reference a specific memory location should be less than
726 /// this value. Those that do must not be less than this value, and can
727 /// be used with SelectionDAG::getMemIntrinsicNode.
728 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+200;
730 //===--------------------------------------------------------------------===//
731 /// MemIndexedMode enum - This enum defines the load / store indexed
732 /// addressing modes.
734 /// UNINDEXED "Normal" load / store. The effective address is already
735 /// computed and is available in the base pointer. The offset
736 /// operand is always undefined. In addition to producing a
737 /// chain, an unindexed load produces one value (result of the
738 /// load); an unindexed store does not produce a value.
740 /// PRE_INC Similar to the unindexed mode where the effective address is
741 /// PRE_DEC the value of the base pointer add / subtract the offset.
742 /// It considers the computation as being folded into the load /
743 /// store operation (i.e. the load / store does the address
744 /// computation as well as performing the memory transaction).
745 /// The base operand is always undefined. In addition to
746 /// producing a chain, pre-indexed load produces two values
747 /// (result of the load and the result of the address
748 /// computation); a pre-indexed store produces one value (result
749 /// of the address computation).
751 /// POST_INC The effective address is the value of the base pointer. The
752 /// POST_DEC value of the offset operand is then added to / subtracted
753 /// from the base after memory transaction. In addition to
754 /// producing a chain, post-indexed load produces two values
755 /// (the result of the load and the result of the base +/- offset
756 /// computation); a post-indexed store produces one value (the
757 /// the result of the base +/- offset computation).
758 enum MemIndexedMode {
767 //===--------------------------------------------------------------------===//
768 /// LoadExtType enum - This enum defines the three variants of LOADEXT
769 /// (load with extension).
771 /// SEXTLOAD loads the integer operand and sign extends it to a larger
772 /// integer result type.
773 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
774 /// integer result type.
775 /// EXTLOAD is used for two things: floating point extending loads and
776 /// integer extending loads [the top bits are undefined].
785 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
787 //===--------------------------------------------------------------------===//
788 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
789 /// below work out, when considering SETFALSE (something that never exists
790 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
791 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
792 /// to. If the "N" column is 1, the result of the comparison is undefined if
793 /// the input is a NAN.
795 /// All of these (except for the 'always folded ops') should be handled for
796 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
797 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
799 /// Note that these are laid out in a specific order to allow bit-twiddling
800 /// to transform conditions.
802 // Opcode N U L G E Intuitive operation
803 SETFALSE, // 0 0 0 0 Always false (always folded)
804 SETOEQ, // 0 0 0 1 True if ordered and equal
805 SETOGT, // 0 0 1 0 True if ordered and greater than
806 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
807 SETOLT, // 0 1 0 0 True if ordered and less than
808 SETOLE, // 0 1 0 1 True if ordered and less than or equal
809 SETONE, // 0 1 1 0 True if ordered and operands are unequal
810 SETO, // 0 1 1 1 True if ordered (no nans)
811 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
812 SETUEQ, // 1 0 0 1 True if unordered or equal
813 SETUGT, // 1 0 1 0 True if unordered or greater than
814 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
815 SETULT, // 1 1 0 0 True if unordered or less than
816 SETULE, // 1 1 0 1 True if unordered, less than, or equal
817 SETUNE, // 1 1 1 0 True if unordered or not equal
818 SETTRUE, // 1 1 1 1 Always true (always folded)
819 // Don't care operations: undefined if the input is a nan.
820 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
821 SETEQ, // 1 X 0 0 1 True if equal
822 SETGT, // 1 X 0 1 0 True if greater than
823 SETGE, // 1 X 0 1 1 True if greater than or equal
824 SETLT, // 1 X 1 0 0 True if less than
825 SETLE, // 1 X 1 0 1 True if less than or equal
826 SETNE, // 1 X 1 1 0 True if not equal
827 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
829 SETCC_INVALID // Marker value.
832 /// isSignedIntSetCC - Return true if this is a setcc instruction that
833 /// performs a signed comparison when used with integer operands.
834 inline bool isSignedIntSetCC(CondCode Code) {
835 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
838 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that
839 /// performs an unsigned comparison when used with integer operands.
840 inline bool isUnsignedIntSetCC(CondCode Code) {
841 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
844 /// isTrueWhenEqual - Return true if the specified condition returns true if
845 /// the two operands to the condition are equal. Note that if one of the two
846 /// operands is a NaN, this value is meaningless.
847 inline bool isTrueWhenEqual(CondCode Cond) {
848 return ((int)Cond & 1) != 0;
851 /// getUnorderedFlavor - This function returns 0 if the condition is always
852 /// false if an operand is a NaN, 1 if the condition is always true if the
853 /// operand is a NaN, and 2 if the condition is undefined if the operand is a
855 inline unsigned getUnorderedFlavor(CondCode Cond) {
856 return ((int)Cond >> 3) & 3;
859 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
860 /// 'op' is a valid SetCC operation.
861 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
863 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
864 /// when given the operation for (X op Y).
865 CondCode getSetCCSwappedOperands(CondCode Operation);
867 /// getSetCCOrOperation - Return the result of a logical OR between different
868 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This
869 /// function returns SETCC_INVALID if it is not possible to represent the
870 /// resultant comparison.
871 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
873 /// getSetCCAndOperation - Return the result of a logical AND between
874 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
875 /// function returns SETCC_INVALID if it is not possible to represent the
876 /// resultant comparison.
877 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
879 //===--------------------------------------------------------------------===//
880 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
883 CVT_FF, /// Float from Float
884 CVT_FS, /// Float from Signed
885 CVT_FU, /// Float from Unsigned
886 CVT_SF, /// Signed from Float
887 CVT_UF, /// Unsigned from Float
888 CVT_SS, /// Signed from Signed
889 CVT_SU, /// Signed from Unsigned
890 CVT_US, /// Unsigned from Signed
891 CVT_UU, /// Unsigned from Unsigned
892 CVT_INVALID /// Marker - Invalid opcode
895 } // end llvm::ISD namespace
897 } // end llvm namespace