include/llvm/CodeGen/InstrScheduling.h

   1 // $Id$ -*- C++ -*-
   2 //***************************************************************************
   3 // File:
   4 //      InstrScheduling.h
   5 //
   6 // Purpose:
   7 //
   8 // History:
   9 //      7/23/01  -  Vikram Adve  -  Created
  10 //***************************************************************************
  11
  12 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
  13 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
  14
  15 #include "llvm/Support/CommandLine.h"
  16 #include "llvm/CodeGen/MachineInstr.h"
  17
  18 class Method;
  19 class SchedulingManager;
  20 class TargetMachine;
  21 class MachineSchedInfo;
  22
  23 // Debug option levels for instruction scheduling
  24 enum SchedDebugLevel_t {
  25   Sched_NoDebugInfo,
  26   Sched_PrintMachineCode,
  27   Sched_PrintSchedTrace,
  28   Sched_PrintSchedGraphs,
  29 };
  30
  31 extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
  32
  33
  34
  35 //---------------------------------------------------------------------------
  36 // Function: ScheduleInstructionsWithSSA
  37 //
  38 // Purpose:
  39 //   Entry point for instruction scheduling on SSA form.
  40 //   Schedules the machine instructions generated by instruction selection.
  41 //   Assumes that register allocation has not been done, i.e., operands
  42 //   are still in SSA form.
  43 //---------------------------------------------------------------------------
  44
  45 bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target);
  46
  47
  48 //---------------------------------------------------------------------------
  49 // Function: ScheduleInstructions
  50 //
  51 // Purpose:
  52 //   Entry point for instruction scheduling on machine code.
  53 //   Schedules the machine instructions generated by instruction selection.
  54 //   Assumes that register allocation has been done.
  55 //---------------------------------------------------------------------------
  56
  57 // Not implemented yet.
  58 bool            ScheduleInstructions            (Method* method,
  59                                                  const TargetMachine &Target);
  60
  61 //---------------------------------------------------------------------------
  62 // Function: instrIsFeasible
  63 //
  64 // Purpose:
  65 //   Used by the priority analysis to filter out instructions
  66 //   that are not feasible to issue in the current cycle.
  67 //   Should only be used during schedule construction..
  68 //---------------------------------------------------------------------------
  69
  70 bool            instrIsFeasible                 (const SchedulingManager& S,
  71                                                  MachineOpCode opCode);
  72 #endif