2 //***************************************************************************
9 // 7/23/01 - Vikram Adve - Created
10 //***************************************************************************
12 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
13 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
15 #include "llvm/Support/CommandLine.h"
16 #include "llvm/CodeGen/MachineInstr.h"
19 class SchedulingManager;
21 class MachineSchedInfo;
23 // Debug option levels for instruction scheduling
24 enum SchedDebugLevel_t {
26 Sched_PrintMachineCode,
27 Sched_PrintSchedTrace,
28 Sched_PrintSchedGraphs,
31 extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
35 //---------------------------------------------------------------------------
36 // Function: ScheduleInstructionsWithSSA
39 // Entry point for instruction scheduling on SSA form.
40 // Schedules the machine instructions generated by instruction selection.
41 // Assumes that register allocation has not been done, i.e., operands
42 // are still in SSA form.
43 //---------------------------------------------------------------------------
45 bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target,
46 const MachineSchedInfo &schedInfo);
48 //---------------------------------------------------------------------------
49 // Function: ScheduleInstructions
52 // Entry point for instruction scheduling on machine code.
53 // Schedules the machine instructions generated by instruction selection.
54 // Assumes that register allocation has been done.
55 //---------------------------------------------------------------------------
57 // Not implemented yet.
58 bool ScheduleInstructions (Method* method,
59 const TargetMachine &Target);
61 //---------------------------------------------------------------------------
62 // Function: instrIsFeasible
65 // Used by the priority analysis to filter out instructions
66 // that are not feasible to issue in the current cycle.
67 // Should only be used during schedule construction..
68 //---------------------------------------------------------------------------
70 bool instrIsFeasible (const SchedulingManager& S,
71 MachineOpCode opCode);