include/llvm/CodeGen/InstrScheduling.h

   1 // $Id$ -*- C++ -*-
   2 //***************************************************************************
   3 // File:
   4 //      InstrScheduling.h
   5 //
   6 // Purpose:
   7 //
   8 // History:
   9 //      7/23/01  -  Vikram Adve  -  Created
  10 //***************************************************************************
  11
  12 #ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
  13 #define LLVM_CODEGEN_INSTR_SCHEDULING_H
  14
  15 #include "llvm/CodeGen/MachineInstr.h"
  16
  17 class Method;
  18 class SchedulingManager;
  19 class TargetMachine;
  20 class MachineSchedInfo;
  21
  22 //---------------------------------------------------------------------------
  23 // Function: ScheduleInstructionsWithSSA
  24 //
  25 // Purpose:
  26 //   Entry point for instruction scheduling on SSA form.
  27 //   Schedules the machine instructions generated by instruction selection.
  28 //   Assumes that register allocation has not been done, i.e., operands
  29 //   are still in SSA form.
  30 //---------------------------------------------------------------------------
  31
  32 bool ScheduleInstructionsWithSSA(Method *M, const TargetMachine &Target);
  33
  34
  35 //---------------------------------------------------------------------------
  36 // Function: ScheduleInstructions
  37 //
  38 // Purpose:
  39 //   Entry point for instruction scheduling on machine code.
  40 //   Schedules the machine instructions generated by instruction selection.
  41 //   Assumes that register allocation has been done.
  42 //---------------------------------------------------------------------------
  43
  44 // Not implemented yet.
  45 bool            ScheduleInstructions            (Method* method,
  46                                                  const TargetMachine &Target);
  47
  48 //---------------------------------------------------------------------------
  49 // Function: instrIsFeasible
  50 //
  51 // Purpose:
  52 //   Used by the priority analysis to filter out instructions
  53 //   that are not feasible to issue in the current cycle.
  54 //   Should only be used during schedule construction..
  55 //---------------------------------------------------------------------------
  56
  57 bool            instrIsFeasible                 (const SchedulingManager& S,
  58                                                  MachineOpCode opCode);
  59 #endif