1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// CloneMIs - A list of clones as result of re-materialization.
67 std::vector<MachineInstr*> CloneMIs;
70 static char ID; // Pass identification, replacement for typeid
71 LiveIntervals() : MachineFunctionPass(ID) {
72 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
75 // Calculate the spill weight to assign to a single instruction.
76 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
78 typedef Reg2IntervalMap::iterator iterator;
79 typedef Reg2IntervalMap::const_iterator const_iterator;
80 const_iterator begin() const { return r2iMap_.begin(); }
81 const_iterator end() const { return r2iMap_.end(); }
82 iterator begin() { return r2iMap_.begin(); }
83 iterator end() { return r2iMap_.end(); }
84 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
86 LiveInterval &getInterval(unsigned reg) {
87 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
88 assert(I != r2iMap_.end() && "Interval does not exist for register");
92 const LiveInterval &getInterval(unsigned reg) const {
93 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
94 assert(I != r2iMap_.end() && "Interval does not exist for register");
98 bool hasInterval(unsigned reg) const {
99 return r2iMap_.count(reg);
102 /// isAllocatable - is the physical register reg allocatable in the current
104 bool isAllocatable(unsigned reg) const {
105 return allocatableRegs_.test(reg);
108 /// getScaledIntervalSize - get the size of an interval in "units,"
109 /// where every function is composed of one thousand units. This
110 /// measure scales properly with empty index slots in the function.
111 double getScaledIntervalSize(LiveInterval& I) {
112 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
115 /// getFuncInstructionCount - Return the number of instructions in the
116 /// current function.
117 unsigned getFuncInstructionCount() {
118 return indexes_->getFunctionSize();
121 /// getApproximateInstructionCount - computes an estimate of the number
122 /// of instructions in a given LiveInterval.
123 unsigned getApproximateInstructionCount(LiveInterval& I) {
124 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
125 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
129 LiveInterval &getOrCreateInterval(unsigned reg) {
130 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
131 if (I == r2iMap_.end())
132 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
136 /// dupInterval - Duplicate a live interval. The caller is responsible for
137 /// managing the allocated memory.
138 LiveInterval *dupInterval(LiveInterval *li);
140 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
141 /// adds a live range from that instruction to the end of its MBB.
142 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
143 MachineInstr* startInst);
145 /// shrinkToUses - After removing some uses of a register, shrink its live
146 /// range to just the remaining uses. This method does not compute reaching
147 /// defs for new uses, and it doesn't remove dead defs.
148 /// Dead PHIDef values are marked as unused.
149 /// New dead machine instructions are added to the dead vector.
150 /// Return true if the interval may have been separated into multiple
151 /// connected components.
152 bool shrinkToUses(LiveInterval *li,
153 SmallVectorImpl<MachineInstr*> *dead = 0);
157 void removeInterval(unsigned Reg) {
158 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
163 SlotIndexes *getSlotIndexes() const {
167 SlotIndex getZeroIndex() const {
168 return indexes_->getZeroIndex();
171 SlotIndex getInvalidIndex() const {
172 return indexes_->getInvalidIndex();
175 /// isNotInMIMap - returns true if the specified machine instr has been
176 /// removed or was never entered in the map.
177 bool isNotInMIMap(const MachineInstr* Instr) const {
178 return !indexes_->hasIndex(Instr);
181 /// Returns the base index of the given instruction.
182 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
183 return indexes_->getInstructionIndex(instr);
186 /// Returns the instruction associated with the given index.
187 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
188 return indexes_->getInstructionFromIndex(index);
191 /// Return the first index in the given basic block.
192 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
193 return indexes_->getMBBStartIdx(mbb);
196 /// Return the last index in the given basic block.
197 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
198 return indexes_->getMBBEndIdx(mbb);
201 bool isLiveInToMBB(const LiveInterval &li,
202 const MachineBasicBlock *mbb) const {
203 return li.liveAt(getMBBStartIdx(mbb));
206 LiveRange* findEnteringRange(LiveInterval &li,
207 const MachineBasicBlock *mbb) {
208 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
211 bool isLiveOutOfMBB(const LiveInterval &li,
212 const MachineBasicBlock *mbb) const {
213 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
216 LiveRange* findExitingRange(LiveInterval &li,
217 const MachineBasicBlock *mbb) {
218 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
221 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
222 return indexes_->getMBBFromIndex(index);
225 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
226 return indexes_->insertMachineInstrInMaps(MI);
229 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
230 indexes_->removeMachineInstrFromMaps(MI);
233 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
234 indexes_->replaceMachineInstrInMaps(MI, NewMI);
237 void InsertMBBInMaps(MachineBasicBlock *MBB) {
238 indexes_->insertMBBInMaps(MBB);
241 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
242 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
243 return indexes_->findLiveInMBBs(Start, End, MBBs);
247 indexes_->renumberIndexes();
250 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
252 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
253 virtual void releaseMemory();
255 /// runOnMachineFunction - pass entry point
256 virtual bool runOnMachineFunction(MachineFunction&);
258 /// print - Implement the dump method.
259 virtual void print(raw_ostream &O, const Module* = 0) const;
261 /// isReMaterializable - Returns true if every definition of MI of every
262 /// val# of the specified interval is re-materializable. Also returns true
263 /// by reference if all of the defs are load instructions.
264 bool isReMaterializable(const LiveInterval &li,
265 const SmallVectorImpl<LiveInterval*> *SpillIs,
268 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
269 /// within a single basic block.
270 bool intervalIsInOneMBB(const LiveInterval &li) const;
272 /// getLastSplitPoint - Return the last possible insertion point in mbb for
273 /// spilling and splitting code. This is the first terminator, or the call
274 /// instruction if li is live into a landing pad successor.
275 MachineBasicBlock::iterator getLastSplitPoint(const LiveInterval &li,
276 MachineBasicBlock *mbb) const;
278 /// addKillFlags - Add kill flags to any instruction that kills a virtual
283 /// computeIntervals - Compute live intervals.
284 void computeIntervals();
286 /// handleRegisterDef - update intervals for a register def
287 /// (calls handlePhysicalRegisterDef and
288 /// handleVirtualRegisterDef)
289 void handleRegisterDef(MachineBasicBlock *MBB,
290 MachineBasicBlock::iterator MI,
292 MachineOperand& MO, unsigned MOIdx);
294 /// isPartialRedef - Return true if the specified def at the specific index
295 /// is partially re-defining the specified live interval. A common case of
296 /// this is a definition of the sub-register.
297 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
298 LiveInterval &interval);
300 /// handleVirtualRegisterDef - update intervals for a virtual
302 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
303 MachineBasicBlock::iterator MI,
304 SlotIndex MIIdx, MachineOperand& MO,
306 LiveInterval& interval);
308 /// handlePhysicalRegisterDef - update intervals for a physical register
310 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
311 MachineBasicBlock::iterator mi,
312 SlotIndex MIIdx, MachineOperand& MO,
313 LiveInterval &interval,
314 MachineInstr *CopyMI);
316 /// handleLiveInRegister - Create interval for a livein register.
317 void handleLiveInRegister(MachineBasicBlock* mbb,
319 LiveInterval &interval, bool isAlias = false);
321 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
322 /// only allow one) virtual register operand, then its uses are implicitly
323 /// using the register. Returns the virtual register.
324 unsigned getReMatImplicitUse(const LiveInterval &li,
325 MachineInstr *MI) const;
327 /// isValNoAvailableAt - Return true if the val# of the specified interval
328 /// which reaches the given instruction also reaches the specified use
330 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
331 SlotIndex UseIdx) const;
333 /// isReMaterializable - Returns true if the definition MI of the specified
334 /// val# of the specified interval is re-materializable. Also returns true
335 /// by reference if the def is a load.
336 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
338 const SmallVectorImpl<LiveInterval*> *SpillIs,
341 static LiveInterval* createInterval(unsigned Reg);
343 void printInstrs(raw_ostream &O) const;
344 void dumpInstrs() const;
346 } // End llvm namespace