1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// CloneMIs - A list of clones as result of re-materialization.
67 std::vector<MachineInstr*> CloneMIs;
70 static char ID; // Pass identification, replacement for typeid
71 LiveIntervals() : MachineFunctionPass(&ID) {}
73 // Calculate the spill weight to assign to a single instruction.
74 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
76 // After summing the spill weights of all defs and uses, the final weight
77 // should be normalized, dividing the weight of the interval by its size.
78 // This encourages spilling of intervals that are large and have few uses,
79 // and discourages spilling of small intervals with many uses.
80 void normalizeSpillWeight(LiveInterval &li) {
81 li.weight /= getApproximateInstructionCount(li) + 25;
84 typedef Reg2IntervalMap::iterator iterator;
85 typedef Reg2IntervalMap::const_iterator const_iterator;
86 const_iterator begin() const { return r2iMap_.begin(); }
87 const_iterator end() const { return r2iMap_.end(); }
88 iterator begin() { return r2iMap_.begin(); }
89 iterator end() { return r2iMap_.end(); }
90 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
92 LiveInterval &getInterval(unsigned reg) {
93 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
94 assert(I != r2iMap_.end() && "Interval does not exist for register");
98 const LiveInterval &getInterval(unsigned reg) const {
99 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
100 assert(I != r2iMap_.end() && "Interval does not exist for register");
104 bool hasInterval(unsigned reg) const {
105 return r2iMap_.count(reg);
108 /// getScaledIntervalSize - get the size of an interval in "units,"
109 /// where every function is composed of one thousand units. This
110 /// measure scales properly with empty index slots in the function.
111 double getScaledIntervalSize(LiveInterval& I) {
112 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
115 /// getFuncInstructionCount - Return the number of instructions in the
116 /// current function.
117 unsigned getFuncInstructionCount() {
118 return indexes_->getFunctionSize();
121 /// getApproximateInstructionCount - computes an estimate of the number
122 /// of instructions in a given LiveInterval.
123 unsigned getApproximateInstructionCount(LiveInterval& I) {
124 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
125 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
128 /// conflictsWithPhysReg - Returns true if the specified register is used or
129 /// defined during the duration of the specified interval. Copies to and
130 /// from li.reg are allowed. This method is only able to analyze simple
131 /// ranges that stay within a single basic block. Anything else is
132 /// considered a conflict.
133 bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
136 /// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
137 /// it checks for sub-register reference and it can check use as well.
138 bool conflictsWithSubPhysRegRef(LiveInterval &li, unsigned Reg,
140 SmallPtrSet<MachineInstr*,32> &JoinedCopies);
143 LiveInterval &getOrCreateInterval(unsigned reg) {
144 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
145 if (I == r2iMap_.end())
146 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
150 /// dupInterval - Duplicate a live interval. The caller is responsible for
151 /// managing the allocated memory.
152 LiveInterval *dupInterval(LiveInterval *li);
154 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
155 /// adds a live range from that instruction to the end of its MBB.
156 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
157 MachineInstr* startInst);
161 void removeInterval(unsigned Reg) {
162 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
167 SlotIndex getZeroIndex() const {
168 return indexes_->getZeroIndex();
171 SlotIndex getInvalidIndex() const {
172 return indexes_->getInvalidIndex();
175 /// isNotInMIMap - returns true if the specified machine instr has been
176 /// removed or was never entered in the map.
177 bool isNotInMIMap(const MachineInstr* Instr) const {
178 return !indexes_->hasIndex(Instr);
181 /// Returns the base index of the given instruction.
182 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
183 return indexes_->getInstructionIndex(instr);
186 /// Returns the instruction associated with the given index.
187 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
188 return indexes_->getInstructionFromIndex(index);
191 /// Return the first index in the given basic block.
192 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
193 return indexes_->getMBBStartIdx(mbb);
196 /// Return the last index in the given basic block.
197 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
198 return indexes_->getMBBEndIdx(mbb);
201 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
202 return indexes_->getMBBFromIndex(index);
205 SlotIndex getMBBTerminatorGap(const MachineBasicBlock *mbb) {
206 return indexes_->getTerminatorGap(mbb);
209 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
210 return indexes_->insertMachineInstrInMaps(MI);
213 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
214 indexes_->removeMachineInstrFromMaps(MI);
217 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
218 indexes_->replaceMachineInstrInMaps(MI, NewMI);
221 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
222 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
223 return indexes_->findLiveInMBBs(Start, End, MBBs);
227 indexes_->renumberIndexes();
230 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
232 /// getVNInfoSourceReg - Helper function that parses the specified VNInfo
233 /// copy field and returns the source register that defines it.
234 unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
236 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
237 virtual void releaseMemory();
239 /// runOnMachineFunction - pass entry point
240 virtual bool runOnMachineFunction(MachineFunction&);
242 /// print - Implement the dump method.
243 virtual void print(raw_ostream &O, const Module* = 0) const;
245 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
246 /// the given interval. FIXME: It also returns the weight of the spill slot
247 /// (if any is created) by reference. This is temporary.
248 std::vector<LiveInterval*>
249 addIntervalsForSpills(const LiveInterval& i,
250 SmallVectorImpl<LiveInterval*> &SpillIs,
251 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
253 /// addIntervalsForSpillsFast - Quickly create new intervals for spilled
254 /// defs / uses without remat or splitting.
255 std::vector<LiveInterval*>
256 addIntervalsForSpillsFast(const LiveInterval &li,
257 const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
259 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
260 /// around all defs and uses of the specified interval. Return true if it
261 /// was able to cut its interval.
262 bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
263 unsigned PhysReg, VirtRegMap &vrm);
265 /// isReMaterializable - Returns true if every definition of MI of every
266 /// val# of the specified interval is re-materializable. Also returns true
267 /// by reference if all of the defs are load instructions.
268 bool isReMaterializable(const LiveInterval &li,
269 SmallVectorImpl<LiveInterval*> &SpillIs,
272 /// isReMaterializable - Returns true if the definition MI of the specified
273 /// val# of the specified interval is re-materializable.
274 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
277 /// getRepresentativeReg - Find the largest super register of the specified
278 /// physical register.
279 unsigned getRepresentativeReg(unsigned Reg) const;
281 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
282 /// specified interval that conflicts with the specified physical register.
283 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
284 unsigned PhysReg) const;
286 /// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
287 /// marker to implicit_def defs and their uses.
288 void processImplicitDefs();
290 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
291 /// within a single basic block.
292 bool intervalIsInOneMBB(const LiveInterval &li) const;
295 /// computeIntervals - Compute live intervals.
296 void computeIntervals();
298 /// handleRegisterDef - update intervals for a register def
299 /// (calls handlePhysicalRegisterDef and
300 /// handleVirtualRegisterDef)
301 void handleRegisterDef(MachineBasicBlock *MBB,
302 MachineBasicBlock::iterator MI,
304 MachineOperand& MO, unsigned MOIdx);
306 /// isPartialRedef - Return true if the specified def at the specific index
307 /// is partially re-defining the specified live interval. A common case of
308 /// this is a definition of the sub-register.
309 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
310 LiveInterval &interval);
312 /// handleVirtualRegisterDef - update intervals for a virtual
314 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
315 MachineBasicBlock::iterator MI,
316 SlotIndex MIIdx, MachineOperand& MO,
318 LiveInterval& interval);
320 /// handlePhysicalRegisterDef - update intervals for a physical register
322 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
323 MachineBasicBlock::iterator mi,
324 SlotIndex MIIdx, MachineOperand& MO,
325 LiveInterval &interval,
326 MachineInstr *CopyMI);
328 /// handleLiveInRegister - Create interval for a livein register.
329 void handleLiveInRegister(MachineBasicBlock* mbb,
331 LiveInterval &interval, bool isAlias = false);
333 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
334 /// only allow one) virtual register operand, then its uses are implicitly
335 /// using the register. Returns the virtual register.
336 unsigned getReMatImplicitUse(const LiveInterval &li,
337 MachineInstr *MI) const;
339 /// isValNoAvailableAt - Return true if the val# of the specified interval
340 /// which reaches the given instruction also reaches the specified use
342 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
343 SlotIndex UseIdx) const;
345 /// isReMaterializable - Returns true if the definition MI of the specified
346 /// val# of the specified interval is re-materializable. Also returns true
347 /// by reference if the def is a load.
348 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
350 SmallVectorImpl<LiveInterval*> &SpillIs,
353 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
354 /// slot / to reg or any rematerialized load into ith operand of specified
355 /// MI. If it is successul, MI is updated with the newly created MI and
357 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
358 MachineInstr *DefMI, SlotIndex InstrIdx,
359 SmallVector<unsigned, 2> &Ops,
360 bool isSS, int FrameIndex, unsigned Reg);
362 /// canFoldMemoryOperand - Return true if the specified load / store
363 /// folding is possible.
364 bool canFoldMemoryOperand(MachineInstr *MI,
365 SmallVector<unsigned, 2> &Ops,
366 bool ReMatLoadSS) const;
368 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
369 /// VNInfo that's after the specified index but is within the basic block.
370 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
371 MachineBasicBlock *MBB,
372 SlotIndex Idx) const;
374 /// hasAllocatableSuperReg - Return true if the specified physical register
375 /// has any super register that's allocatable.
376 bool hasAllocatableSuperReg(unsigned Reg) const;
378 /// SRInfo - Spill / restore info.
383 SRInfo(SlotIndex i, unsigned vr, bool f)
384 : index(i), vreg(vr), canFold(f) {}
387 bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
388 BitVector &RestoreMBBs,
389 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
390 void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
391 BitVector &RestoreMBBs,
392 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
394 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
395 /// spilled and create empty intervals for their uses.
396 void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
397 const TargetRegisterClass* rc,
398 std::vector<LiveInterval*> &NewLIs);
400 /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
401 /// interval on to-be re-materialized operands of MI) with new register.
402 void rewriteImplicitOps(const LiveInterval &li,
403 MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
405 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
406 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
408 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
409 bool TrySplit, SlotIndex index, SlotIndex end,
410 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
411 unsigned Slot, int LdSlot,
412 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
413 VirtRegMap &vrm, const TargetRegisterClass* rc,
414 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
415 unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
416 DenseMap<unsigned,unsigned> &MBBVRegsMap,
417 std::vector<LiveInterval*> &NewLIs);
418 void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
419 LiveInterval::Ranges::const_iterator &I,
420 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
421 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
422 VirtRegMap &vrm, const TargetRegisterClass* rc,
423 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
424 BitVector &SpillMBBs,
425 DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
426 BitVector &RestoreMBBs,
427 DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
428 DenseMap<unsigned,unsigned> &MBBVRegsMap,
429 std::vector<LiveInterval*> &NewLIs);
431 // Normalize the spill weight of all the intervals in NewLIs.
432 void normalizeSpillWeights(std::vector<LiveInterval*> &NewLIs);
434 static LiveInterval* createInterval(unsigned Reg);
436 void printInstrs(raw_ostream &O) const;
437 void dumpInstrs() const;
439 } // End llvm namespace