1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' abd there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/IndexedMap.h"
33 class TargetInstrInfo;
34 class TargetRegisterClass;
37 class LiveIntervals : public MachineFunctionPass {
39 const TargetMachine* tm_;
40 const MRegisterInfo* mri_;
41 const TargetInstrInfo* tii_;
44 /// MBB2IdxMap - The index of the first instruction in the specified basic
46 std::vector<unsigned> MBB2IdxMap;
48 typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
51 typedef std::vector<MachineInstr*> Index2MiMap;
54 typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
55 Reg2IntervalMap r2iMap_;
57 typedef IndexedMap<unsigned> Reg2RegMap;
60 BitVector allocatableRegs_;
61 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
63 /// JoinedLIs - Keep track which register intervals have been coalesced
64 /// with other intervals.
70 unsigned SrcReg, DstReg;
72 CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
89 static unsigned getBaseIndex(unsigned index) {
90 return index - (index % InstrSlots::NUM);
92 static unsigned getBoundaryIndex(unsigned index) {
93 return getBaseIndex(index + InstrSlots::NUM - 1);
95 static unsigned getLoadIndex(unsigned index) {
96 return getBaseIndex(index) + InstrSlots::LOAD;
98 static unsigned getUseIndex(unsigned index) {
99 return getBaseIndex(index) + InstrSlots::USE;
101 static unsigned getDefIndex(unsigned index) {
102 return getBaseIndex(index) + InstrSlots::DEF;
104 static unsigned getStoreIndex(unsigned index) {
105 return getBaseIndex(index) + InstrSlots::STORE;
108 typedef Reg2IntervalMap::iterator iterator;
109 typedef Reg2IntervalMap::const_iterator const_iterator;
110 const_iterator begin() const { return r2iMap_.begin(); }
111 const_iterator end() const { return r2iMap_.end(); }
112 iterator begin() { return r2iMap_.begin(); }
113 iterator end() { return r2iMap_.end(); }
114 unsigned getNumIntervals() const { return r2iMap_.size(); }
116 LiveInterval &getInterval(unsigned reg) {
117 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
118 assert(I != r2iMap_.end() && "Interval does not exist for register");
122 const LiveInterval &getInterval(unsigned reg) const {
123 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
124 assert(I != r2iMap_.end() && "Interval does not exist for register");
128 bool hasInterval(unsigned reg) const {
129 return r2iMap_.count(reg);
132 /// getMBBStartIdx - Return the base index of the first instruction in the
133 /// specified MachineBasicBlock.
134 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
135 return getMBBStartIdx(MBB->getNumber());
138 unsigned getMBBStartIdx(unsigned MBBNo) const {
139 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
140 return MBB2IdxMap[MBBNo];
143 /// getInstructionIndex - returns the base index of instr
144 unsigned getInstructionIndex(MachineInstr* instr) const {
145 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
146 assert(it != mi2iMap_.end() && "Invalid instruction!");
150 /// getInstructionFromIndex - given an index in any slot of an
151 /// instruction return a pointer the instruction
152 MachineInstr* getInstructionFromIndex(unsigned index) const {
153 index /= InstrSlots::NUM; // convert index to vector index
154 assert(index < i2miMap_.size() &&
155 "index does not correspond to an instruction");
156 return i2miMap_[index];
159 std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
163 /// CreateNewLiveInterval - Create a new live interval with the given live
164 /// ranges. The new live interval will have an infinite spill weight.
165 LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
166 const std::vector<LiveRange> &LRs);
168 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
169 virtual void releaseMemory();
171 /// runOnMachineFunction - pass entry point
172 virtual bool runOnMachineFunction(MachineFunction&);
174 /// print - Implement the dump method.
175 virtual void print(std::ostream &O, const Module* = 0) const;
176 void print(std::ostream *O, const Module* M = 0) const {
181 /// isRemoved - returns true if the specified machine instr has been
183 bool isRemoved(MachineInstr* instr) const {
184 return !mi2iMap_.count(instr);
187 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
189 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
190 // remove index -> MachineInstr and
191 // MachineInstr -> index mappings
192 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
193 if (mi2i != mi2iMap_.end()) {
194 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
195 mi2iMap_.erase(mi2i);
199 /// computeIntervals - Compute live intervals.
200 void computeIntervals();
202 /// joinIntervals - join compatible live intervals
203 void joinIntervals();
205 /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
206 /// copies that cannot yet be coallesced into the "TryAgain" list.
207 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
208 std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
210 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
211 /// which are the src/dst of the copy instruction CopyMI. This returns true
212 /// if the copy was successfully coallesced away, or if it is never possible
213 /// to coallesce these this copy, due to register constraints. It returns
214 /// false if it is not currently possible to coallesce this interval, but
215 /// it may be possible if other things get coallesced.
216 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
217 bool PhysOnly = false);
219 /// JoinIntervals - Attempt to join these two intervals. On failure, this
220 /// returns false. Otherwise, if one of the intervals being joined is a
221 /// physreg, this method always canonicalizes DestInt to be it. The output
222 /// "SrcInt" will not have been modified, so we can use this information
223 /// below to update aliases.
224 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS);
226 /// SimpleJoin - Attempt to join the specified interval into this one. The
227 /// caller of this method must guarantee that the RHS only contains a single
228 /// value number and that the RHS is not defined by a copy from this
229 /// interval. This returns false if the intervals are not joinable, or it
230 /// joins them and returns true.
231 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
233 /// handleRegisterDef - update intervals for a register def
234 /// (calls handlePhysicalRegisterDef and
235 /// handleVirtualRegisterDef)
236 void handleRegisterDef(MachineBasicBlock *MBB,
237 MachineBasicBlock::iterator MI, unsigned MIIdx,
240 /// handleVirtualRegisterDef - update intervals for a virtual
242 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
243 MachineBasicBlock::iterator MI,
245 LiveInterval& interval);
247 /// handlePhysicalRegisterDef - update intervals for a physical register
249 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
250 MachineBasicBlock::iterator mi,
252 LiveInterval &interval,
255 /// handleLiveInRegister - Create interval for a livein register.
256 void handleLiveInRegister(MachineBasicBlock* mbb,
258 LiveInterval &interval, bool isAlias = false);
260 /// Return true if the two specified registers belong to different
261 /// register classes. The registers may be either phys or virt regs.
262 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
265 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
266 MachineInstr *CopyMI);
268 /// lastRegisterUse - Returns the last use of the specific register between
269 /// cycles Start and End. It also returns the use operand by reference. It
270 /// returns NULL if there are no uses.
271 MachineInstr *lastRegisterUse(unsigned Reg, unsigned Start, unsigned End,
272 MachineOperand *&MOU);
274 /// findDefOperand - Returns the MachineOperand that is a def of the specific
275 /// register. It returns NULL if the def is not found.
276 MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
278 /// unsetRegisterKill - Unset IsKill property of all uses of the specific
279 /// register of the specific instruction.
280 void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
282 /// hasRegisterDef - True if the instruction defines the specific register.
284 bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
286 static LiveInterval createInterval(unsigned Reg);
288 void removeInterval(unsigned Reg) {
292 LiveInterval &getOrCreateInterval(unsigned reg) {
293 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
294 if (I == r2iMap_.end())
295 I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
299 /// rep - returns the representative of this register
300 unsigned rep(unsigned Reg) {
301 unsigned Rep = r2rMap_[Reg];
303 return r2rMap_[Reg] = rep(Rep);
307 void printRegName(unsigned reg) const;
310 } // End llvm namespace