1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' abd there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/IndexedMap.h"
33 class TargetInstrInfo;
34 class TargetRegisterClass;
37 class LiveIntervals : public MachineFunctionPass {
39 const TargetMachine* tm_;
40 const MRegisterInfo* mri_;
41 const TargetInstrInfo* tii_;
44 /// MBB2IdxMap - The index of the first instruction in the specified basic
46 std::vector<unsigned> MBB2IdxMap;
48 typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
51 typedef std::vector<MachineInstr*> Index2MiMap;
54 typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
55 Reg2IntervalMap r2iMap_;
57 typedef IndexedMap<unsigned> Reg2RegMap;
60 BitVector allocatableRegs_;
61 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
63 /// JoinedLIs - Keep track which register intervals have been coalesced
64 /// with other intervals.
68 static char ID; // Pass identifcation, replacement for typeid
69 LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
73 unsigned SrcReg, DstReg;
75 CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
92 static unsigned getBaseIndex(unsigned index) {
93 return index - (index % InstrSlots::NUM);
95 static unsigned getBoundaryIndex(unsigned index) {
96 return getBaseIndex(index + InstrSlots::NUM - 1);
98 static unsigned getLoadIndex(unsigned index) {
99 return getBaseIndex(index) + InstrSlots::LOAD;
101 static unsigned getUseIndex(unsigned index) {
102 return getBaseIndex(index) + InstrSlots::USE;
104 static unsigned getDefIndex(unsigned index) {
105 return getBaseIndex(index) + InstrSlots::DEF;
107 static unsigned getStoreIndex(unsigned index) {
108 return getBaseIndex(index) + InstrSlots::STORE;
111 typedef Reg2IntervalMap::iterator iterator;
112 typedef Reg2IntervalMap::const_iterator const_iterator;
113 const_iterator begin() const { return r2iMap_.begin(); }
114 const_iterator end() const { return r2iMap_.end(); }
115 iterator begin() { return r2iMap_.begin(); }
116 iterator end() { return r2iMap_.end(); }
117 unsigned getNumIntervals() const { return r2iMap_.size(); }
119 LiveInterval &getInterval(unsigned reg) {
120 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
121 assert(I != r2iMap_.end() && "Interval does not exist for register");
125 const LiveInterval &getInterval(unsigned reg) const {
126 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
127 assert(I != r2iMap_.end() && "Interval does not exist for register");
131 bool hasInterval(unsigned reg) const {
132 return r2iMap_.count(reg);
135 /// getMBBStartIdx - Return the base index of the first instruction in the
136 /// specified MachineBasicBlock.
137 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
138 return getMBBStartIdx(MBB->getNumber());
141 unsigned getMBBStartIdx(unsigned MBBNo) const {
142 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
143 return MBB2IdxMap[MBBNo];
146 /// getInstructionIndex - returns the base index of instr
147 unsigned getInstructionIndex(MachineInstr* instr) const {
148 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
149 assert(it != mi2iMap_.end() && "Invalid instruction!");
153 /// getInstructionFromIndex - given an index in any slot of an
154 /// instruction return a pointer the instruction
155 MachineInstr* getInstructionFromIndex(unsigned index) const {
156 index /= InstrSlots::NUM; // convert index to vector index
157 assert(index < i2miMap_.size() &&
158 "index does not correspond to an instruction");
159 return i2miMap_[index];
162 std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
166 /// CreateNewLiveInterval - Create a new live interval with the given live
167 /// ranges. The new live interval will have an infinite spill weight.
168 LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
169 const std::vector<LiveRange> &LRs);
171 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
172 virtual void releaseMemory();
174 /// runOnMachineFunction - pass entry point
175 virtual bool runOnMachineFunction(MachineFunction&);
177 /// print - Implement the dump method.
178 virtual void print(std::ostream &O, const Module* = 0) const;
179 void print(std::ostream *O, const Module* M = 0) const {
184 /// isRemoved - returns true if the specified machine instr has been
186 bool isRemoved(MachineInstr* instr) const {
187 return !mi2iMap_.count(instr);
190 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
192 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
193 // remove index -> MachineInstr and
194 // MachineInstr -> index mappings
195 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
196 if (mi2i != mi2iMap_.end()) {
197 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
198 mi2iMap_.erase(mi2i);
202 /// computeIntervals - Compute live intervals.
203 void computeIntervals();
205 /// joinIntervals - join compatible live intervals
206 void joinIntervals();
208 /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
209 /// copies that cannot yet be coallesced into the "TryAgain" list.
210 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
211 std::vector<CopyRec> *TryAgain, bool PhysOnly = false);
213 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
214 /// which are the src/dst of the copy instruction CopyMI. This returns true
215 /// if the copy was successfully coallesced away, or if it is never possible
216 /// to coallesce these this copy, due to register constraints. It returns
217 /// false if it is not currently possible to coallesce this interval, but
218 /// it may be possible if other things get coallesced.
219 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg,
220 bool PhysOnly = false);
222 /// JoinIntervals - Attempt to join these two intervals. On failure, this
223 /// returns false. Otherwise, if one of the intervals being joined is a
224 /// physreg, this method always canonicalizes DestInt to be it. The output
225 /// "SrcInt" will not have been modified, so we can use this information
226 /// below to update aliases.
227 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS);
229 /// SimpleJoin - Attempt to join the specified interval into this one. The
230 /// caller of this method must guarantee that the RHS only contains a single
231 /// value number and that the RHS is not defined by a copy from this
232 /// interval. This returns false if the intervals are not joinable, or it
233 /// joins them and returns true.
234 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
236 /// handleRegisterDef - update intervals for a register def
237 /// (calls handlePhysicalRegisterDef and
238 /// handleVirtualRegisterDef)
239 void handleRegisterDef(MachineBasicBlock *MBB,
240 MachineBasicBlock::iterator MI, unsigned MIIdx,
243 /// handleVirtualRegisterDef - update intervals for a virtual
245 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
246 MachineBasicBlock::iterator MI,
248 LiveInterval& interval);
250 /// handlePhysicalRegisterDef - update intervals for a physical register
252 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
253 MachineBasicBlock::iterator mi,
255 LiveInterval &interval,
258 /// handleLiveInRegister - Create interval for a livein register.
259 void handleLiveInRegister(MachineBasicBlock* mbb,
261 LiveInterval &interval, bool isAlias = false);
263 /// Return true if the two specified registers belong to different
264 /// register classes. The registers may be either phys or virt regs.
265 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
268 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
269 MachineInstr *CopyMI);
271 /// lastRegisterUse - Returns the last use of the specific register between
272 /// cycles Start and End. It also returns the use operand by reference. It
273 /// returns NULL if there are no uses.
274 MachineInstr *lastRegisterUse(unsigned Reg, unsigned Start, unsigned End,
275 MachineOperand *&MOU);
277 /// findDefOperand - Returns the MachineOperand that is a def of the specific
278 /// register. It returns NULL if the def is not found.
279 MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg);
281 /// unsetRegisterKill - Unset IsKill property of all uses of the specific
282 /// register of the specific instruction.
283 void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
285 /// hasRegisterDef - True if the instruction defines the specific register.
287 bool hasRegisterDef(MachineInstr *MI, unsigned Reg);
289 static LiveInterval createInterval(unsigned Reg);
291 void removeInterval(unsigned Reg) {
295 LiveInterval &getOrCreateInterval(unsigned reg) {
296 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
297 if (I == r2iMap_.end())
298 I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
302 /// rep - returns the representative of this register
303 unsigned rep(unsigned Reg) {
304 unsigned Rep = r2rMap_[Reg];
306 return r2rMap_[Reg] = rep(Rep);
310 void printRegName(unsigned reg) const;
313 } // End llvm namespace