1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' abd there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "LiveInterval.h"
32 class LiveIntervals : public MachineFunctionPass {
34 const TargetMachine* tm_;
35 const MRegisterInfo* mri_;
38 typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
41 typedef std::vector<MachineInstr*> Index2MiMap;
44 typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
45 Reg2IntervalMap r2iMap_;
47 typedef std::map<unsigned, unsigned> Reg2RegMap;
50 std::vector<bool> allocatableRegs_;
64 static unsigned getBaseIndex(unsigned index) {
65 return index - (index % InstrSlots::NUM);
67 static unsigned getBoundaryIndex(unsigned index) {
68 return getBaseIndex(index + InstrSlots::NUM - 1);
70 static unsigned getLoadIndex(unsigned index) {
71 return getBaseIndex(index) + InstrSlots::LOAD;
73 static unsigned getUseIndex(unsigned index) {
74 return getBaseIndex(index) + InstrSlots::USE;
76 static unsigned getDefIndex(unsigned index) {
77 return getBaseIndex(index) + InstrSlots::DEF;
79 static unsigned getStoreIndex(unsigned index) {
80 return getBaseIndex(index) + InstrSlots::STORE;
83 // FIXME: this should really be a const_iterator
84 typedef Reg2IntervalMap::iterator iterator;
85 iterator begin() { return r2iMap_.begin(); }
86 iterator end() { return r2iMap_.end(); }
87 unsigned getNumIntervals() const { return r2iMap_.size(); }
89 LiveInterval &getInterval(unsigned reg) {
90 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
91 assert(I != r2iMap_.end() && "Interval does not exist for register");
95 const LiveInterval &getInterval(unsigned reg) const {
96 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
97 assert(I != r2iMap_.end() && "Interval does not exist for register");
101 /// getInstructionIndex - returns the base index of instr
102 unsigned getInstructionIndex(MachineInstr* instr) const {
103 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
104 assert(it != mi2iMap_.end() && "Invalid instruction!");
108 /// getInstructionFromIndex - given an index in any slot of an
109 /// instruction return a pointer the instruction
110 MachineInstr* getInstructionFromIndex(unsigned index) const {
111 index /= InstrSlots::NUM; // convert index to vector index
112 assert(index < i2miMap_.size() &&
113 "index does not correspond to an instruction");
114 return i2miMap_[index];
117 std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
121 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
122 virtual void releaseMemory();
124 /// runOnMachineFunction - pass entry point
125 virtual bool runOnMachineFunction(MachineFunction&);
128 /// computeIntervals - compute live intervals
129 void computeIntervals();
131 /// joinIntervals - join compatible live intervals
132 void joinIntervals();
134 /// joinIntervalsInMachineBB - Join intervals based on move
135 /// instructions in the specified basic block.
136 void joinIntervalsInMachineBB(MachineBasicBlock *MBB);
138 /// handleRegisterDef - update intervals for a register def
139 /// (calls handlePhysicalRegisterDef and
140 /// handleVirtualRegisterDef)
141 void handleRegisterDef(MachineBasicBlock* mbb,
142 MachineBasicBlock::iterator mi,
145 /// handleVirtualRegisterDef - update intervals for a virtual
147 void handleVirtualRegisterDef(MachineBasicBlock* mbb,
148 MachineBasicBlock::iterator mi,
149 LiveInterval& interval);
151 /// handlePhysicalRegisterDef - update intervals for a
152 /// physical register def
153 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
154 MachineBasicBlock::iterator mi,
155 LiveInterval& interval);
157 /// Return true if the two specified registers belong to different
158 /// register classes. The registers may be either phys or virt regs.
159 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
161 bool overlapsAliases(const LiveInterval *lhs,
162 const LiveInterval *rhs) const;
164 static LiveInterval createInterval(unsigned Reg);
166 LiveInterval &getOrCreateInterval(unsigned reg) {
167 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
168 if (I == r2iMap_.end())
169 I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
173 /// rep - returns the representative of this register
174 unsigned rep(unsigned reg) {
175 Reg2RegMap::iterator it = r2rMap_.find(reg);
176 if (it != r2rMap_.end())
177 return it->second = rep(it->second);
181 void printRegName(unsigned reg) const;
184 } // End llvm namespace