1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/SlotIndexes.h"
29 #include "llvm/Support/Allocator.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
37 extern cl::opt<bool> UseSegmentSetForPhysRegs;
44 class MachineDominatorTree;
45 class MachineLoopInfo;
46 class TargetRegisterInfo;
47 class MachineRegisterInfo;
48 class TargetInstrInfo;
49 class TargetRegisterClass;
51 class MachineBlockFrequencyInfo;
53 class LiveIntervals : public MachineFunctionPass {
55 MachineRegisterInfo* MRI;
56 const TargetRegisterInfo* TRI;
57 const TargetInstrInfo* TII;
60 MachineDominatorTree *DomTree;
61 LiveRangeCalc *LRCalc;
63 /// Special pool allocator for VNInfo's (LiveInterval val#).
65 VNInfo::Allocator VNInfoAllocator;
67 /// Live interval pointers for all the virtual registers.
68 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
70 /// RegMaskSlots - Sorted list of instructions with register mask operands.
71 /// Always use the 'r' slot, RegMasks are normal clobbers, not early
73 SmallVector<SlotIndex, 8> RegMaskSlots;
75 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
76 /// pointer to the corresponding register mask. This pointer can be
79 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
80 /// unsigned OpNum = findRegMaskOperand(MI);
81 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
83 /// This is kept in a separate vector partly because some standard
84 /// libraries don't support lower_bound() with mixed objects, partly to
85 /// improve locality when searching in RegMaskSlots.
86 /// Also see the comment in LiveInterval::find().
87 SmallVector<const uint32_t*, 8> RegMaskBits;
89 /// For each basic block number, keep (begin, size) pairs indexing into the
90 /// RegMaskSlots and RegMaskBits arrays.
91 /// Note that basic block numbers may not be layout contiguous, that's why
92 /// we can't just keep track of the first register mask in each basic
94 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
96 /// Keeps a live range set for each register unit to track fixed physreg
98 SmallVector<LiveRange*, 0> RegUnitRanges;
101 static char ID; // Pass identification, replacement for typeid
103 ~LiveIntervals() override;
105 // Calculate the spill weight to assign to a single instruction.
106 static float getSpillWeight(bool isDef, bool isUse,
107 const MachineBlockFrequencyInfo *MBFI,
108 const MachineInstr *Instr);
110 LiveInterval &getInterval(unsigned Reg) {
111 if (hasInterval(Reg))
112 return *VirtRegIntervals[Reg];
114 return createAndComputeVirtRegInterval(Reg);
117 const LiveInterval &getInterval(unsigned Reg) const {
118 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
121 bool hasInterval(unsigned Reg) const {
122 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
125 // Interval creation.
126 LiveInterval &createEmptyInterval(unsigned Reg) {
127 assert(!hasInterval(Reg) && "Interval already exists!");
128 VirtRegIntervals.grow(Reg);
129 VirtRegIntervals[Reg] = createInterval(Reg);
130 return *VirtRegIntervals[Reg];
133 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
134 LiveInterval &LI = createEmptyInterval(Reg);
135 computeVirtRegInterval(LI);
140 void removeInterval(unsigned Reg) {
141 delete VirtRegIntervals[Reg];
142 VirtRegIntervals[Reg] = nullptr;
145 /// Given a register and an instruction, adds a live segment from that
146 /// instruction to the end of its MBB.
147 LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
148 MachineInstr* startInst);
150 /// shrinkToUses - After removing some uses of a register, shrink its live
151 /// range to just the remaining uses. This method does not compute reaching
152 /// defs for new uses, and it doesn't remove dead defs.
153 /// Dead PHIDef values are marked as unused.
154 /// New dead machine instructions are added to the dead vector.
155 /// Return true if the interval may have been separated into multiple
156 /// connected components.
157 bool shrinkToUses(LiveInterval *li,
158 SmallVectorImpl<MachineInstr*> *dead = nullptr);
160 /// Specialized version of
161 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
162 /// that works on a subregister live range and only looks at uses matching
163 /// the lane mask of the subregister range.
164 void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
166 /// extendToIndices - Extend the live range of LI to reach all points in
167 /// Indices. The points in the Indices array must be jointly dominated by
168 /// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
170 /// If a SlotIndex in Indices is the end index of a basic block, LI will be
171 /// extended to be live out of the basic block.
173 /// See also LiveRangeCalc::extend().
174 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
177 /// If @p LR has a live value at @p Kill, prune its live range by removing
178 /// any liveness reachable from Kill. Add live range end points to
179 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
180 /// value's live range.
182 /// Calling pruneValue() and extendToIndices() can be used to reconstruct
183 /// SSA form after adding defs to a virtual register.
184 void pruneValue(LiveRange &LR, SlotIndex Kill,
185 SmallVectorImpl<SlotIndex> *EndPoints);
187 SlotIndexes *getSlotIndexes() const {
191 AliasAnalysis *getAliasAnalysis() const {
195 /// isNotInMIMap - returns true if the specified machine instr has been
196 /// removed or was never entered in the map.
197 bool isNotInMIMap(const MachineInstr* Instr) const {
198 return !Indexes->hasIndex(Instr);
201 /// Returns the base index of the given instruction.
202 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
203 return Indexes->getInstructionIndex(instr);
206 /// Returns the instruction associated with the given index.
207 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
208 return Indexes->getInstructionFromIndex(index);
211 /// Return the first index in the given basic block.
212 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
213 return Indexes->getMBBStartIdx(mbb);
216 /// Return the last index in the given basic block.
217 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
218 return Indexes->getMBBEndIdx(mbb);
221 bool isLiveInToMBB(const LiveRange &LR,
222 const MachineBasicBlock *mbb) const {
223 return LR.liveAt(getMBBStartIdx(mbb));
226 bool isLiveOutOfMBB(const LiveRange &LR,
227 const MachineBasicBlock *mbb) const {
228 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
231 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
232 return Indexes->getMBBFromIndex(index);
235 void insertMBBInMaps(MachineBasicBlock *MBB) {
236 Indexes->insertMBBInMaps(MBB);
237 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
238 "Blocks must be added in order.");
239 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
242 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
243 return Indexes->insertMachineInstrInMaps(MI);
246 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
247 MachineBasicBlock::iterator E) {
248 for (MachineBasicBlock::iterator I = B; I != E; ++I)
249 Indexes->insertMachineInstrInMaps(I);
252 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
253 Indexes->removeMachineInstrFromMaps(MI);
256 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
257 Indexes->replaceMachineInstrInMaps(MI, NewMI);
260 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
261 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
262 return Indexes->findLiveInMBBs(Start, End, MBBs);
265 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
267 void getAnalysisUsage(AnalysisUsage &AU) const override;
268 void releaseMemory() override;
270 /// runOnMachineFunction - pass entry point
271 bool runOnMachineFunction(MachineFunction&) override;
273 /// print - Implement the dump method.
274 void print(raw_ostream &O, const Module* = nullptr) const override;
276 /// intervalIsInOneMBB - If LI is confined to a single basic block, return
277 /// a pointer to that block. If LI is live in to or out of any block,
279 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
281 /// Returns true if VNI is killed by any PHI-def values in LI.
282 /// This may conservatively return true to avoid expensive computations.
283 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
285 /// addKillFlags - Add kill flags to any instruction that kills a virtual
287 void addKillFlags(const VirtRegMap*);
289 /// handleMove - call this method to notify LiveIntervals that
290 /// instruction 'mi' has been moved within a basic block. This will update
291 /// the live intervals for all operands of mi. Moves between basic blocks
292 /// are not supported.
294 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
295 void handleMove(MachineInstr* MI, bool UpdateFlags = false);
297 /// moveIntoBundle - Update intervals for operands of MI so that they
298 /// begin/end on the SlotIndex for BundleStart.
300 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
302 /// Requires MI and BundleStart to have SlotIndexes, and assumes
303 /// existing liveness is accurate. BundleStart should be the first
304 /// instruction in the Bundle.
305 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
306 bool UpdateFlags = false);
308 /// repairIntervalsInRange - Update live intervals for instructions in a
309 /// range of iterators. It is intended for use after target hooks that may
310 /// insert or remove instructions, and is only efficient for a small number
313 /// OrigRegs is a vector of registers that were originally used by the
314 /// instructions in the range between the two iterators.
316 /// Currently, the only only changes that are supported are simple removal
317 /// and addition of uses.
318 void repairIntervalsInRange(MachineBasicBlock *MBB,
319 MachineBasicBlock::iterator Begin,
320 MachineBasicBlock::iterator End,
321 ArrayRef<unsigned> OrigRegs);
323 // Register mask functions.
325 // Machine instructions may use a register mask operand to indicate that a
326 // large number of registers are clobbered by the instruction. This is
327 // typically used for calls.
329 // For compile time performance reasons, these clobbers are not recorded in
330 // the live intervals for individual physical registers. Instead,
331 // LiveIntervalAnalysis maintains a sorted list of instructions with
332 // register mask operands.
334 /// getRegMaskSlots - Returns a sorted array of slot indices of all
335 /// instructions with register mask operands.
336 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
338 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
339 /// instructions with register mask operands in the basic block numbered
341 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
342 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
343 return getRegMaskSlots().slice(P.first, P.second);
346 /// getRegMaskBits() - Returns an array of register mask pointers
347 /// corresponding to getRegMaskSlots().
348 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
350 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
351 /// to getRegMaskSlotsInBlock(MBBNum).
352 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
353 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
354 return getRegMaskBits().slice(P.first, P.second);
357 /// checkRegMaskInterference - Test if LI is live across any register mask
358 /// instructions, and compute a bit mask of physical registers that are not
359 /// clobbered by any of them.
361 /// Returns false if LI doesn't cross any register mask instructions. In
362 /// that case, the bit vector is not filled in.
363 bool checkRegMaskInterference(LiveInterval &LI,
364 BitVector &UsableRegs);
366 // Register unit functions.
368 // Fixed interference occurs when MachineInstrs use physregs directly
369 // instead of virtual registers. This typically happens when passing
370 // arguments to a function call, or when instructions require operands in
373 // Each physreg has one or more register units, see MCRegisterInfo. We
374 // track liveness per register unit to handle aliasing registers more
377 /// getRegUnit - Return the live range for Unit.
378 /// It will be computed if it doesn't exist.
379 LiveRange &getRegUnit(unsigned Unit) {
380 LiveRange *LR = RegUnitRanges[Unit];
382 // Compute missing ranges on demand.
383 // Use segment set to speed-up initial computation of the live range.
384 RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
385 computeRegUnitRange(*LR, Unit);
390 /// getCachedRegUnit - Return the live range for Unit if it has already
391 /// been computed, or NULL if it hasn't been computed yet.
392 LiveRange *getCachedRegUnit(unsigned Unit) {
393 return RegUnitRanges[Unit];
396 const LiveRange *getCachedRegUnit(unsigned Unit) const {
397 return RegUnitRanges[Unit];
400 /// Remove value numbers and related live segments starting at position
401 /// @p Pos that are part of any liverange of physical register @p Reg or one
402 /// of its subregisters.
403 void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
405 /// Remove value number and related live segments of @p LI and its subranges
406 /// that start at position @p Pos.
407 void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
410 /// Compute live intervals for all virtual registers.
411 void computeVirtRegs();
413 /// Compute RegMaskSlots and RegMaskBits.
414 void computeRegMasks();
416 /// Walk the values in @p LI and check for dead values:
417 /// - Dead PHIDef values are marked as unused.
418 /// - Dead operands are marked as such.
419 /// - Completely dead machine instructions are added to the @p dead vector
420 /// if it is not nullptr.
421 /// Returns true if any PHI value numbers have been removed which may
422 /// have separated the interval into multiple connected components.
423 bool computeDeadValues(LiveInterval &LI,
424 SmallVectorImpl<MachineInstr*> *dead);
426 static LiveInterval* createInterval(unsigned Reg);
428 void printInstrs(raw_ostream &O) const;
429 void dumpInstrs() const;
431 void computeLiveInRegUnits();
432 void computeRegUnitRange(LiveRange&, unsigned Unit);
433 void computeVirtRegInterval(LiveInterval&);
436 /// Helper function for repairIntervalsInRange(), walks backwards and
437 /// creates/modifies live segments in @p LR to match the operands found.
438 /// Only full operands or operands with subregisters matching @p LaneMask
440 void repairOldRegInRange(MachineBasicBlock::iterator Begin,
441 MachineBasicBlock::iterator End,
442 const SlotIndex endIdx, LiveRange &LR,
443 unsigned Reg, unsigned LaneMask = ~0u);
447 } // End llvm namespace