1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
67 static char ID; // Pass identification, replacement for typeid
68 LiveIntervals() : MachineFunctionPass(ID) {
69 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
72 // Calculate the spill weight to assign to a single instruction.
73 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
75 typedef Reg2IntervalMap::iterator iterator;
76 typedef Reg2IntervalMap::const_iterator const_iterator;
77 const_iterator begin() const { return r2iMap_.begin(); }
78 const_iterator end() const { return r2iMap_.end(); }
79 iterator begin() { return r2iMap_.begin(); }
80 iterator end() { return r2iMap_.end(); }
81 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
83 LiveInterval &getInterval(unsigned reg) {
84 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
85 assert(I != r2iMap_.end() && "Interval does not exist for register");
89 const LiveInterval &getInterval(unsigned reg) const {
90 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
91 assert(I != r2iMap_.end() && "Interval does not exist for register");
95 bool hasInterval(unsigned reg) const {
96 return r2iMap_.count(reg);
99 /// isAllocatable - is the physical register reg allocatable in the current
101 bool isAllocatable(unsigned reg) const {
102 return allocatableRegs_.test(reg);
105 /// getScaledIntervalSize - get the size of an interval in "units,"
106 /// where every function is composed of one thousand units. This
107 /// measure scales properly with empty index slots in the function.
108 double getScaledIntervalSize(LiveInterval& I) {
109 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
112 /// getFuncInstructionCount - Return the number of instructions in the
113 /// current function.
114 unsigned getFuncInstructionCount() {
115 return indexes_->getFunctionSize();
118 /// getApproximateInstructionCount - computes an estimate of the number
119 /// of instructions in a given LiveInterval.
120 unsigned getApproximateInstructionCount(LiveInterval& I) {
121 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
122 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
126 LiveInterval &getOrCreateInterval(unsigned reg) {
127 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
128 if (I == r2iMap_.end())
129 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
133 /// dupInterval - Duplicate a live interval. The caller is responsible for
134 /// managing the allocated memory.
135 LiveInterval *dupInterval(LiveInterval *li);
137 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
138 /// adds a live range from that instruction to the end of its MBB.
139 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
140 MachineInstr* startInst);
142 /// shrinkToUses - After removing some uses of a register, shrink its live
143 /// range to just the remaining uses. This method does not compute reaching
144 /// defs for new uses, and it doesn't remove dead defs.
145 /// Dead PHIDef values are marked as unused.
146 /// New dead machine instructions are added to the dead vector.
147 /// Return true if the interval may have been separated into multiple
148 /// connected components.
149 bool shrinkToUses(LiveInterval *li,
150 SmallVectorImpl<MachineInstr*> *dead = 0);
154 void removeInterval(unsigned Reg) {
155 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
160 SlotIndexes *getSlotIndexes() const {
164 SlotIndex getZeroIndex() const {
165 return indexes_->getZeroIndex();
168 SlotIndex getInvalidIndex() const {
169 return indexes_->getInvalidIndex();
172 /// isNotInMIMap - returns true if the specified machine instr has been
173 /// removed or was never entered in the map.
174 bool isNotInMIMap(const MachineInstr* Instr) const {
175 return !indexes_->hasIndex(Instr);
178 /// Returns the base index of the given instruction.
179 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
180 return indexes_->getInstructionIndex(instr);
183 /// Returns the instruction associated with the given index.
184 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
185 return indexes_->getInstructionFromIndex(index);
188 /// Return the first index in the given basic block.
189 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
190 return indexes_->getMBBStartIdx(mbb);
193 /// Return the last index in the given basic block.
194 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
195 return indexes_->getMBBEndIdx(mbb);
198 bool isLiveInToMBB(const LiveInterval &li,
199 const MachineBasicBlock *mbb) const {
200 return li.liveAt(getMBBStartIdx(mbb));
203 LiveRange* findEnteringRange(LiveInterval &li,
204 const MachineBasicBlock *mbb) {
205 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
208 bool isLiveOutOfMBB(const LiveInterval &li,
209 const MachineBasicBlock *mbb) const {
210 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
213 LiveRange* findExitingRange(LiveInterval &li,
214 const MachineBasicBlock *mbb) {
215 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
218 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
219 return indexes_->getMBBFromIndex(index);
222 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
223 return indexes_->insertMachineInstrInMaps(MI);
226 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
227 indexes_->removeMachineInstrFromMaps(MI);
230 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
231 indexes_->replaceMachineInstrInMaps(MI, NewMI);
234 void InsertMBBInMaps(MachineBasicBlock *MBB) {
235 indexes_->insertMBBInMaps(MBB);
238 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
239 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
240 return indexes_->findLiveInMBBs(Start, End, MBBs);
244 indexes_->renumberIndexes();
247 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
249 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
250 virtual void releaseMemory();
252 /// runOnMachineFunction - pass entry point
253 virtual bool runOnMachineFunction(MachineFunction&);
255 /// print - Implement the dump method.
256 virtual void print(raw_ostream &O, const Module* = 0) const;
258 /// isReMaterializable - Returns true if every definition of MI of every
259 /// val# of the specified interval is re-materializable. Also returns true
260 /// by reference if all of the defs are load instructions.
261 bool isReMaterializable(const LiveInterval &li,
262 const SmallVectorImpl<LiveInterval*> *SpillIs,
265 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
266 /// within a single basic block.
267 bool intervalIsInOneMBB(const LiveInterval &li) const;
269 /// addKillFlags - Add kill flags to any instruction that kills a virtual
273 /// moveInstr - Move MachineInstr mi to insertPt, updating the live
274 /// intervals of mi's operands to reflect the new position. The insertion
275 /// point can be above or below mi, but must be in the same basic block.
276 void moveInstr(MachineBasicBlock::iterator insertPt, MachineInstr* mi);
279 /// computeIntervals - Compute live intervals.
280 void computeIntervals();
282 /// handleRegisterDef - update intervals for a register def
283 /// (calls handlePhysicalRegisterDef and
284 /// handleVirtualRegisterDef)
285 void handleRegisterDef(MachineBasicBlock *MBB,
286 MachineBasicBlock::iterator MI,
288 MachineOperand& MO, unsigned MOIdx);
290 /// isPartialRedef - Return true if the specified def at the specific index
291 /// is partially re-defining the specified live interval. A common case of
292 /// this is a definition of the sub-register.
293 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
294 LiveInterval &interval);
296 /// handleVirtualRegisterDef - update intervals for a virtual
298 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
299 MachineBasicBlock::iterator MI,
300 SlotIndex MIIdx, MachineOperand& MO,
302 LiveInterval& interval);
304 /// handlePhysicalRegisterDef - update intervals for a physical register
306 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
307 MachineBasicBlock::iterator mi,
308 SlotIndex MIIdx, MachineOperand& MO,
309 LiveInterval &interval,
310 MachineInstr *CopyMI);
312 /// handleLiveInRegister - Create interval for a livein register.
313 void handleLiveInRegister(MachineBasicBlock* mbb,
315 LiveInterval &interval, bool isAlias = false);
317 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
318 /// only allow one) virtual register operand, then its uses are implicitly
319 /// using the register. Returns the virtual register.
320 unsigned getReMatImplicitUse(const LiveInterval &li,
321 MachineInstr *MI) const;
323 /// isValNoAvailableAt - Return true if the val# of the specified interval
324 /// which reaches the given instruction also reaches the specified use
326 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
327 SlotIndex UseIdx) const;
329 /// isReMaterializable - Returns true if the definition MI of the specified
330 /// val# of the specified interval is re-materializable. Also returns true
331 /// by reference if the def is a load.
332 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
334 const SmallVectorImpl<LiveInterval*> *SpillIs,
337 static LiveInterval* createInterval(unsigned Reg);
339 void printInstrs(raw_ostream &O) const;
340 void dumpInstrs() const;
342 } // End llvm namespace