1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/SlotIndexes.h"
29 #include "llvm/Support/Allocator.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
41 class MachineDominatorTree;
42 class MachineLoopInfo;
43 class TargetRegisterInfo;
44 class MachineRegisterInfo;
45 class TargetInstrInfo;
46 class TargetRegisterClass;
48 class MachineBlockFrequencyInfo;
50 class LiveIntervals : public MachineFunctionPass {
52 MachineRegisterInfo* MRI;
53 const TargetRegisterInfo* TRI;
54 const TargetInstrInfo* TII;
57 MachineDominatorTree *DomTree;
58 LiveRangeCalc *LRCalc;
60 /// Special pool allocator for VNInfo's (LiveInterval val#).
62 VNInfo::Allocator VNInfoAllocator;
64 /// Live interval pointers for all the virtual registers.
65 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
67 /// RegMaskSlots - Sorted list of instructions with register mask operands.
68 /// Always use the 'r' slot, RegMasks are normal clobbers, not early
70 SmallVector<SlotIndex, 8> RegMaskSlots;
72 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
73 /// pointer to the corresponding register mask. This pointer can be
76 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
77 /// unsigned OpNum = findRegMaskOperand(MI);
78 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
80 /// This is kept in a separate vector partly because some standard
81 /// libraries don't support lower_bound() with mixed objects, partly to
82 /// improve locality when searching in RegMaskSlots.
83 /// Also see the comment in LiveInterval::find().
84 SmallVector<const uint32_t*, 8> RegMaskBits;
86 /// For each basic block number, keep (begin, size) pairs indexing into the
87 /// RegMaskSlots and RegMaskBits arrays.
88 /// Note that basic block numbers may not be layout contiguous, that's why
89 /// we can't just keep track of the first register mask in each basic
91 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
93 /// Keeps a live range set for each register unit to track fixed physreg
95 SmallVector<LiveRange*, 0> RegUnitRanges;
98 static char ID; // Pass identification, replacement for typeid
100 virtual ~LiveIntervals();
102 // Calculate the spill weight to assign to a single instruction.
103 static float getSpillWeight(bool isDef, bool isUse,
104 const MachineBlockFrequencyInfo *MBFI,
105 const MachineInstr *Instr);
107 LiveInterval &getInterval(unsigned Reg) {
108 if (hasInterval(Reg))
109 return *VirtRegIntervals[Reg];
111 return createAndComputeVirtRegInterval(Reg);
114 const LiveInterval &getInterval(unsigned Reg) const {
115 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
118 bool hasInterval(unsigned Reg) const {
119 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
122 // Interval creation.
123 LiveInterval &createEmptyInterval(unsigned Reg) {
124 assert(!hasInterval(Reg) && "Interval already exists!");
125 VirtRegIntervals.grow(Reg);
126 VirtRegIntervals[Reg] = createInterval(Reg);
127 return *VirtRegIntervals[Reg];
130 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
131 LiveInterval &LI = createEmptyInterval(Reg);
132 computeVirtRegInterval(LI);
137 void removeInterval(unsigned Reg) {
138 delete VirtRegIntervals[Reg];
139 VirtRegIntervals[Reg] = nullptr;
142 /// Given a register and an instruction, adds a live segment from that
143 /// instruction to the end of its MBB.
144 LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
145 MachineInstr* startInst);
147 /// shrinkToUses - After removing some uses of a register, shrink its live
148 /// range to just the remaining uses. This method does not compute reaching
149 /// defs for new uses, and it doesn't remove dead defs.
150 /// Dead PHIDef values are marked as unused.
151 /// New dead machine instructions are added to the dead vector.
152 /// Return true if the interval may have been separated into multiple
153 /// connected components.
154 bool shrinkToUses(LiveInterval *li,
155 SmallVectorImpl<MachineInstr*> *dead = nullptr);
157 /// extendToIndices - Extend the live range of LI to reach all points in
158 /// Indices. The points in the Indices array must be jointly dominated by
159 /// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
161 /// If a SlotIndex in Indices is the end index of a basic block, LI will be
162 /// extended to be live out of the basic block.
164 /// See also LiveRangeCalc::extend().
165 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
167 /// pruneValue - If an LI value is live at Kill, prune its live range by
168 /// removing any liveness reachable from Kill. Add live range end points to
169 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
170 /// value's live range.
172 /// Calling pruneValue() and extendToIndices() can be used to reconstruct
173 /// SSA form after adding defs to a virtual register.
174 void pruneValue(LiveInterval *LI, SlotIndex Kill,
175 SmallVectorImpl<SlotIndex> *EndPoints);
177 SlotIndexes *getSlotIndexes() const {
181 AliasAnalysis *getAliasAnalysis() const {
185 /// isNotInMIMap - returns true if the specified machine instr has been
186 /// removed or was never entered in the map.
187 bool isNotInMIMap(const MachineInstr* Instr) const {
188 return !Indexes->hasIndex(Instr);
191 /// Returns the base index of the given instruction.
192 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
193 return Indexes->getInstructionIndex(instr);
196 /// Returns the instruction associated with the given index.
197 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
198 return Indexes->getInstructionFromIndex(index);
201 /// Return the first index in the given basic block.
202 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
203 return Indexes->getMBBStartIdx(mbb);
206 /// Return the last index in the given basic block.
207 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
208 return Indexes->getMBBEndIdx(mbb);
211 bool isLiveInToMBB(const LiveRange &LR,
212 const MachineBasicBlock *mbb) const {
213 return LR.liveAt(getMBBStartIdx(mbb));
216 bool isLiveOutOfMBB(const LiveRange &LR,
217 const MachineBasicBlock *mbb) const {
218 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
221 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
222 return Indexes->getMBBFromIndex(index);
225 void insertMBBInMaps(MachineBasicBlock *MBB) {
226 Indexes->insertMBBInMaps(MBB);
227 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
228 "Blocks must be added in order.");
229 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
232 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
233 return Indexes->insertMachineInstrInMaps(MI);
236 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
237 MachineBasicBlock::iterator E) {
238 for (MachineBasicBlock::iterator I = B; I != E; ++I)
239 Indexes->insertMachineInstrInMaps(I);
242 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
243 Indexes->removeMachineInstrFromMaps(MI);
246 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
247 Indexes->replaceMachineInstrInMaps(MI, NewMI);
250 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
251 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
252 return Indexes->findLiveInMBBs(Start, End, MBBs);
255 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
257 void getAnalysisUsage(AnalysisUsage &AU) const override;
258 void releaseMemory() override;
260 /// runOnMachineFunction - pass entry point
261 bool runOnMachineFunction(MachineFunction&) override;
263 /// print - Implement the dump method.
264 void print(raw_ostream &O, const Module* = nullptr) const override;
266 /// intervalIsInOneMBB - If LI is confined to a single basic block, return
267 /// a pointer to that block. If LI is live in to or out of any block,
269 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
271 /// Returns true if VNI is killed by any PHI-def values in LI.
272 /// This may conservatively return true to avoid expensive computations.
273 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
275 /// addKillFlags - Add kill flags to any instruction that kills a virtual
277 void addKillFlags(const VirtRegMap*);
279 /// handleMove - call this method to notify LiveIntervals that
280 /// instruction 'mi' has been moved within a basic block. This will update
281 /// the live intervals for all operands of mi. Moves between basic blocks
282 /// are not supported.
284 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
285 void handleMove(MachineInstr* MI, bool UpdateFlags = false);
287 /// moveIntoBundle - Update intervals for operands of MI so that they
288 /// begin/end on the SlotIndex for BundleStart.
290 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
292 /// Requires MI and BundleStart to have SlotIndexes, and assumes
293 /// existing liveness is accurate. BundleStart should be the first
294 /// instruction in the Bundle.
295 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
296 bool UpdateFlags = false);
298 /// repairIntervalsInRange - Update live intervals for instructions in a
299 /// range of iterators. It is intended for use after target hooks that may
300 /// insert or remove instructions, and is only efficient for a small number
303 /// OrigRegs is a vector of registers that were originally used by the
304 /// instructions in the range between the two iterators.
306 /// Currently, the only only changes that are supported are simple removal
307 /// and addition of uses.
308 void repairIntervalsInRange(MachineBasicBlock *MBB,
309 MachineBasicBlock::iterator Begin,
310 MachineBasicBlock::iterator End,
311 ArrayRef<unsigned> OrigRegs);
313 // Register mask functions.
315 // Machine instructions may use a register mask operand to indicate that a
316 // large number of registers are clobbered by the instruction. This is
317 // typically used for calls.
319 // For compile time performance reasons, these clobbers are not recorded in
320 // the live intervals for individual physical registers. Instead,
321 // LiveIntervalAnalysis maintains a sorted list of instructions with
322 // register mask operands.
324 /// getRegMaskSlots - Returns a sorted array of slot indices of all
325 /// instructions with register mask operands.
326 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
328 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
329 /// instructions with register mask operands in the basic block numbered
331 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
332 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
333 return getRegMaskSlots().slice(P.first, P.second);
336 /// getRegMaskBits() - Returns an array of register mask pointers
337 /// corresponding to getRegMaskSlots().
338 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
340 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
341 /// to getRegMaskSlotsInBlock(MBBNum).
342 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
343 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
344 return getRegMaskBits().slice(P.first, P.second);
347 /// checkRegMaskInterference - Test if LI is live across any register mask
348 /// instructions, and compute a bit mask of physical registers that are not
349 /// clobbered by any of them.
351 /// Returns false if LI doesn't cross any register mask instructions. In
352 /// that case, the bit vector is not filled in.
353 bool checkRegMaskInterference(LiveInterval &LI,
354 BitVector &UsableRegs);
356 // Register unit functions.
358 // Fixed interference occurs when MachineInstrs use physregs directly
359 // instead of virtual registers. This typically happens when passing
360 // arguments to a function call, or when instructions require operands in
363 // Each physreg has one or more register units, see MCRegisterInfo. We
364 // track liveness per register unit to handle aliasing registers more
367 /// getRegUnit - Return the live range for Unit.
368 /// It will be computed if it doesn't exist.
369 LiveRange &getRegUnit(unsigned Unit) {
370 LiveRange *LR = RegUnitRanges[Unit];
372 // Compute missing ranges on demand.
373 RegUnitRanges[Unit] = LR = new LiveRange();
374 computeRegUnitRange(*LR, Unit);
379 /// getCachedRegUnit - Return the live range for Unit if it has already
380 /// been computed, or NULL if it hasn't been computed yet.
381 LiveRange *getCachedRegUnit(unsigned Unit) {
382 return RegUnitRanges[Unit];
385 const LiveRange *getCachedRegUnit(unsigned Unit) const {
386 return RegUnitRanges[Unit];
390 /// Compute live intervals for all virtual registers.
391 void computeVirtRegs();
393 /// Compute RegMaskSlots and RegMaskBits.
394 void computeRegMasks();
396 /// \brief Walk the values in the @p LR live range and compute which ones
397 /// are dead in live range @p Segments. Dead values are not deleted,
399 /// - Dead PHIDef values are marked as unused.
400 /// - if @p dead != nullptr then dead operands are marked as such and
401 /// completely dead machine instructions are added to the @p dead vector.
402 /// - CanSeparate is set to true if the interval may have been separated
403 /// into multiple connected components.
404 void computeDeadValues(LiveRange &Segments, LiveRange &LR,
405 bool *CanSeparate = nullptr, unsigned Reg = 0,
406 SmallVectorImpl<MachineInstr*> *dead = nullptr);
408 static LiveInterval* createInterval(unsigned Reg);
410 void printInstrs(raw_ostream &O) const;
411 void dumpInstrs() const;
413 void computeLiveInRegUnits();
414 void computeRegUnitRange(LiveRange&, unsigned Unit);
415 void computeVirtRegInterval(LiveInterval&);
417 /// Specialized version of
418 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
419 /// that works on a subregister live range and only looks at uses matching
420 /// the lane mask of the subregister range.
421 bool shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
425 } // End llvm namespace