1 //===-- llvm/CodeGen/LiveRegUnits.h - Live register unit set ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a Set of live register units. This can be used for ad
11 // hoc liveness tracking after register allocation. You can start with the
12 // live-ins/live-outs at the beginning/end of a block and update the information
13 // while walking the instructions inside the block.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_LIVEREGUNITS_H
18 #define LLVM_CODEGEN_LIVEREGUNITS_H
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/MC/MCRegisterInfo.h"
29 /// A set of live register units with functions to track liveness when walking
30 /// backward/forward through a basic block.
32 SmallSet<unsigned, 32> LiveUnits;
35 /// Constructs a new empty LiveRegUnits set.
39 /// Constructs a new LiveRegUnits set by copying @p Other.
40 LiveRegUnits(const LiveRegUnits &Other)
41 : LiveUnits(Other.LiveUnits) {
44 /// Adds a register to the set.
45 void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
46 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
47 LiveUnits.insert(*RUnits);
50 /// Removes a register from the set.
51 void removeReg(unsigned Reg, const MCRegisterInfo &MCRI) {
52 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
53 LiveUnits.erase(*RUnits);
56 /// \brief Removes registers clobbered by the regmask operand @p Op.
57 /// Note that we assume the high bits of a physical super register are not
58 /// preserved unless the instruction has an implicit-use operand reading
59 /// the super-register or a register unit for the upper bits is available.
60 void removeRegsInMask(const MachineOperand &Op,
61 const MCRegisterInfo &MCRI) {
62 const uint32_t *Mask = Op.getRegMask();
64 for (unsigned R = 0; R < MCRI.getNumRegs(); ++R) {
65 if ((*Mask & (1u << Bit)) == 0)
75 /// Returns true if register @p Reg (or one of its super register) is
76 /// contained in the set.
77 bool contains(unsigned Reg, const MCRegisterInfo &MCRI) const {
78 for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) {
79 if (LiveUnits.count(*RUnits))
85 /// Simulates liveness when stepping backwards over an instruction(bundle):
86 /// Defs are removed from the set, uses added.
87 void stepBackward(const MachineInstr &MI, const MCRegisterInfo &MCRI) {
88 // Remove defined registers and regmask kills from the set.
89 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
93 unsigned Reg = O->getReg();
97 } else if (O->isRegMask()) {
98 removeRegsInMask(*O, MCRI);
101 // Add uses to the set.
102 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
103 if (!O->isReg() || !O->readsReg() || O->isUndef())
105 unsigned Reg = O->getReg();
112 /// \brief Simulates liveness when stepping forward over an
113 /// instruction(bundle).
115 /// Uses with kill flag get removed from the set, defs added. If possible
116 /// use StepBackward() instead of this function because some kill flags may
118 void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI) {
119 SmallVector<unsigned, 4> Defs;
120 // Remove killed registers from the set.
121 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
123 unsigned Reg = O->getReg();
133 removeReg(Reg, MCRI);
135 } else if (O->isRegMask()) {
136 removeRegsInMask(*O, MCRI);
139 // Add defs to the set.
140 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
141 addReg(Defs[i], MCRI);
145 /// Adds all registers in the live-in list of block @p BB.
146 void addLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI) {
147 for (MachineBasicBlock::livein_iterator L = BB.livein_begin(),
148 LE = BB.livein_end(); L != LE; ++L) {