1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SparseBitVector.h"
42 class MachineRegisterInfo;
43 class TargetRegisterInfo;
45 class LiveVariables : public MachineFunctionPass {
47 static char ID; // Pass identification, replacement for typeid
48 LiveVariables() : MachineFunctionPass(&ID) {}
50 /// VarInfo - This represents the regions where a virtual register is live in
51 /// the program. We represent this with three different pieces of
52 /// information: the set of blocks in which the instruction is live
53 /// throughout, the set of blocks in which the instruction is actually used,
54 /// and the set of non-phi instructions that are the last users of the value.
56 /// In the common case where a value is defined and killed in the same block,
57 /// There is one killing instruction, and AliveBlocks is empty.
59 /// Otherwise, the value is live out of the block. If the value is live
60 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
61 /// where the liveness range ends are not included in AliveBlocks, instead
62 /// being captured by the Kills set. In these blocks, the value is live into
63 /// the block (unless the value is defined and killed in the same block) and
64 /// lives until the specified instruction. Note that there cannot ever be a
65 /// value whose Kills set contains two instructions from the same basic block.
67 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
68 /// value in one of its predecessor blocks, it is not listed in the kills set,
69 /// but does include the predecessor block in the AliveBlocks set (unless that
70 /// block also defines the value). This leads to the (perfectly sensical)
71 /// situation where a value is defined in a block, and the last use is a phi
72 /// node in the successor. In this case, AliveBlocks is empty (the value is
73 /// not live across any blocks) and Kills is empty (phi nodes are not
74 /// included). This is sensical because the value must be live to the end of
75 /// the block, but is not live in any successor blocks.
77 /// AliveBlocks - Set of blocks in which this value is alive completely
78 /// through. This is a bit set which uses the basic block number as an
81 SparseBitVector<> AliveBlocks;
83 /// NumUses - Number of uses of this register across the entire function.
87 /// Kills - List of MachineInstruction's which are the last use of this
88 /// virtual register (kill it) in their basic block.
90 std::vector<MachineInstr*> Kills;
92 VarInfo() : NumUses(0) {}
94 /// removeKill - Delete a kill corresponding to the specified
95 /// machine instruction. Returns true if there was a kill
96 /// corresponding to this instruction, false otherwise.
97 bool removeKill(MachineInstr *MI) {
98 std::vector<MachineInstr*>::iterator
99 I = std::find(Kills.begin(), Kills.end(), MI);
100 if (I == Kills.end())
110 /// VirtRegInfo - This list is a mapping from virtual register number to
111 /// variable information. FirstVirtualRegister is subtracted from the virtual
112 /// register number before indexing into this list.
114 std::vector<VarInfo> VirtRegInfo;
116 /// ReservedRegisters - This vector keeps track of which registers
117 /// are reserved register which are not allocatable by the target machine.
118 /// We can not track liveness for values that are in this set.
120 BitVector ReservedRegisters;
122 private: // Intermediate data structures
125 MachineRegisterInfo* MRI;
127 const TargetRegisterInfo *TRI;
129 // PhysRegInfo - Keep track of which instruction was the last def of a
130 // physical register. This is a purely local property, because all physical
131 // register references are presumed dead across basic blocks.
132 MachineInstr **PhysRegDef;
134 // PhysRegInfo - Keep track of which instruction was the last use of a
135 // physical register. This is a purely local property, because all physical
136 // register references are presumed dead across basic blocks.
137 MachineInstr **PhysRegUse;
139 SmallVector<unsigned, 4> *PHIVarInfo;
141 // DistanceMap - Keep track the distance of a MI from the start of the
142 // current basic block.
143 DenseMap<MachineInstr*, unsigned> DistanceMap;
145 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
146 /// uses. Pay special attention to the sub-register uses which may come below
147 /// the last use of the whole register.
148 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
150 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
151 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
153 /// FindLastPartialDef - Return the last partial def of the specified register.
154 /// Also returns the sub-register that's defined.
155 MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
157 /// hasRegisterUseBelow - Return true if the specified register is used after
158 /// the current instruction and before it's next definition.
159 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
160 MachineBasicBlock *MBB);
162 /// analyzePHINodes - Gather information about the PHI nodes in here. In
163 /// particular, we want to map the variable information of a virtual
164 /// register which is used in a PHI node. We map that to the BB the vreg
166 void analyzePHINodes(const MachineFunction& Fn);
169 virtual bool runOnMachineFunction(MachineFunction &MF);
171 /// RegisterDefIsDead - Return true if the specified instruction defines the
172 /// specified register, but that definition is dead.
173 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
175 //===--------------------------------------------------------------------===//
176 // API to update live variable information
178 /// replaceKillInstruction - Update register kill info by replacing a kill
179 /// instruction with a new one.
180 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
181 MachineInstr *NewMI);
183 /// addVirtualRegisterKilled - Add information about the fact that the
184 /// specified register is killed after being used by the specified
185 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
187 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
188 bool AddIfNotFound = false) {
189 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
190 getVarInfo(IncomingReg).Kills.push_back(MI);
193 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
194 /// register from the live variable information. Returns true if the
195 /// variable was marked as killed by the specified instruction,
197 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
198 if (!getVarInfo(reg).removeKill(MI))
201 bool Removed = false;
202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
203 MachineOperand &MO = MI->getOperand(i);
204 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
211 assert(Removed && "Register is not used by this instruction!");
215 /// removeVirtualRegistersKilled - Remove all killed info for the specified
217 void removeVirtualRegistersKilled(MachineInstr *MI);
219 /// addVirtualRegisterDead - Add information about the fact that the specified
220 /// register is dead after being used by the specified instruction. If
221 /// AddIfNotFound is true, add a implicit operand if it's not found.
222 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
223 bool AddIfNotFound = false) {
224 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
225 getVarInfo(IncomingReg).Kills.push_back(MI);
228 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
229 /// register from the live variable information. Returns true if the
230 /// variable was marked dead at the specified instruction, false
232 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
233 if (!getVarInfo(reg).removeKill(MI))
236 bool Removed = false;
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 MachineOperand &MO = MI->getOperand(i);
239 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
245 assert(Removed && "Register is not defined by this instruction!");
249 void getAnalysisUsage(AnalysisUsage &AU) const;
251 virtual void releaseMemory() {
255 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
257 VarInfo &getVarInfo(unsigned RegIdx);
259 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
260 MachineBasicBlock *BB);
261 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
262 MachineBasicBlock *BB,
263 std::vector<MachineBasicBlock*> &WorkList);
264 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
265 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
269 } // End llvm namespace