1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/SmallVector.h"
36 #include "llvm/ADT/SparseBitVector.h"
40 class MachineRegisterInfo;
41 class TargetRegisterInfo;
43 class LiveVariables : public MachineFunctionPass {
45 static char ID; // Pass identification, replacement for typeid
46 LiveVariables() : MachineFunctionPass(&ID) {}
48 /// VarInfo - This represents the regions where a virtual register is live in
49 /// the program. We represent this with three different pieces of
50 /// information: the set of blocks in which the instruction is live
51 /// throughout, the set of blocks in which the instruction is actually used,
52 /// and the set of non-phi instructions that are the last users of the value.
54 /// In the common case where a value is defined and killed in the same block,
55 /// There is one killing instruction, and AliveBlocks is empty.
57 /// Otherwise, the value is live out of the block. If the value is live
58 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
59 /// where the liveness range ends are not included in AliveBlocks, instead
60 /// being captured by the Kills set. In these blocks, the value is live into
61 /// the block (unless the value is defined and killed in the same block) and
62 /// lives until the specified instruction. Note that there cannot ever be a
63 /// value whose Kills set contains two instructions from the same basic block.
65 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
66 /// value in one of its predecessor blocks, it is not listed in the kills set,
67 /// but does include the predecessor block in the AliveBlocks set (unless that
68 /// block also defines the value). This leads to the (perfectly sensical)
69 /// situation where a value is defined in a block, and the last use is a phi
70 /// node in the successor. In this case, AliveBlocks is empty (the value is
71 /// not live across any blocks) and Kills is empty (phi nodes are not
72 /// included). This is sensical because the value must be live to the end of
73 /// the block, but is not live in any successor blocks.
75 /// AliveBlocks - Set of blocks in which this value is alive completely
76 /// through. This is a bit set which uses the basic block number as an
79 SparseBitVector<> AliveBlocks;
81 /// NumUses - Number of uses of this register across the entire function.
85 /// Kills - List of MachineInstruction's which are the last use of this
86 /// virtual register (kill it) in their basic block.
88 std::vector<MachineInstr*> Kills;
90 VarInfo() : NumUses(0) {}
92 /// removeKill - Delete a kill corresponding to the specified
93 /// machine instruction. Returns true if there was a kill
94 /// corresponding to this instruction, false otherwise.
95 bool removeKill(MachineInstr *MI) {
96 std::vector<MachineInstr*>::iterator
97 I = std::find(Kills.begin(), Kills.end(), MI);
108 /// VirtRegInfo - This list is a mapping from virtual register number to
109 /// variable information. FirstVirtualRegister is subtracted from the virtual
110 /// register number before indexing into this list.
112 std::vector<VarInfo> VirtRegInfo;
114 /// ReservedRegisters - This vector keeps track of which registers
115 /// are reserved register which are not allocatable by the target machine.
116 /// We can not track liveness for values that are in this set.
118 BitVector ReservedRegisters;
120 private: // Intermediate data structures
123 MachineRegisterInfo* MRI;
125 const TargetRegisterInfo *TRI;
127 // PhysRegInfo - Keep track of which instruction was the last def of a
128 // physical register. This is a purely local property, because all physical
129 // register references are presumed dead across basic blocks.
130 MachineInstr **PhysRegDef;
132 // PhysRegInfo - Keep track of which instruction was the last use of a
133 // physical register. This is a purely local property, because all physical
134 // register references are presumed dead across basic blocks.
135 MachineInstr **PhysRegUse;
137 SmallVector<unsigned, 4> *PHIVarInfo;
139 // DistanceMap - Keep track the distance of a MI from the start of the
140 // current basic block.
141 DenseMap<MachineInstr*, unsigned> DistanceMap;
143 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
144 /// uses. Pay special attention to the sub-register uses which may come below
145 /// the last use of the whole register.
146 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
148 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
149 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
151 /// FindLastPartialDef - Return the last partial def of the specified register.
152 /// Also returns the sub-register that's defined.
153 MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
155 /// hasRegisterUseBelow - Return true if the specified register is used after
156 /// the current instruction and before it's next definition.
157 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
158 MachineBasicBlock *MBB);
160 /// analyzePHINodes - Gather information about the PHI nodes in here. In
161 /// particular, we want to map the variable information of a virtual
162 /// register which is used in a PHI node. We map that to the BB the vreg
164 void analyzePHINodes(const MachineFunction& Fn);
167 virtual bool runOnMachineFunction(MachineFunction &MF);
169 /// RegisterDefIsDead - Return true if the specified instruction defines the
170 /// specified register, but that definition is dead.
171 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
173 //===--------------------------------------------------------------------===//
174 // API to update live variable information
176 /// replaceKillInstruction - Update register kill info by replacing a kill
177 /// instruction with a new one.
178 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
179 MachineInstr *NewMI);
181 /// addVirtualRegisterKilled - Add information about the fact that the
182 /// specified register is killed after being used by the specified
183 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
185 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
186 bool AddIfNotFound = false) {
187 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
188 getVarInfo(IncomingReg).Kills.push_back(MI);
191 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
192 /// register from the live variable information. Returns true if the
193 /// variable was marked as killed by the specified instruction,
195 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
196 if (!getVarInfo(reg).removeKill(MI))
199 bool Removed = false;
200 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
201 MachineOperand &MO = MI->getOperand(i);
202 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
209 assert(Removed && "Register is not used by this instruction!");
213 /// removeVirtualRegistersKilled - Remove all killed info for the specified
215 void removeVirtualRegistersKilled(MachineInstr *MI);
217 /// addVirtualRegisterDead - Add information about the fact that the specified
218 /// register is dead after being used by the specified instruction. If
219 /// AddIfNotFound is true, add a implicit operand if it's not found.
220 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
221 bool AddIfNotFound = false) {
222 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
223 getVarInfo(IncomingReg).Kills.push_back(MI);
226 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
227 /// register from the live variable information. Returns true if the
228 /// variable was marked dead at the specified instruction, false
230 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
231 if (!getVarInfo(reg).removeKill(MI))
234 bool Removed = false;
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = MI->getOperand(i);
237 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
243 assert(Removed && "Register is not defined by this instruction!");
247 void getAnalysisUsage(AnalysisUsage &AU) const;
249 virtual void releaseMemory() {
253 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
255 VarInfo &getVarInfo(unsigned RegIdx);
257 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
258 MachineBasicBlock *BB);
259 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
260 MachineBasicBlock *BB,
261 std::vector<MachineBasicBlock*> &WorkList);
262 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
263 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
267 } // End llvm namespace