1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/IndexedMap.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/ADT/SparseBitVector.h"
45 class MachineRegisterInfo;
46 class TargetRegisterInfo;
48 class LiveVariables : public MachineFunctionPass {
50 static char ID; // Pass identification, replacement for typeid
51 LiveVariables() : MachineFunctionPass(ID) {
52 initializeLiveVariablesPass(*PassRegistry::getPassRegistry());
55 /// VarInfo - This represents the regions where a virtual register is live in
56 /// the program. We represent this with three different pieces of
57 /// information: the set of blocks in which the instruction is live
58 /// throughout, the set of blocks in which the instruction is actually used,
59 /// and the set of non-phi instructions that are the last users of the value.
61 /// In the common case where a value is defined and killed in the same block,
62 /// There is one killing instruction, and AliveBlocks is empty.
64 /// Otherwise, the value is live out of the block. If the value is live
65 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
66 /// where the liveness range ends are not included in AliveBlocks, instead
67 /// being captured by the Kills set. In these blocks, the value is live into
68 /// the block (unless the value is defined and killed in the same block) and
69 /// lives until the specified instruction. Note that there cannot ever be a
70 /// value whose Kills set contains two instructions from the same basic block.
72 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
73 /// value in one of its predecessor blocks, it is not listed in the kills set,
74 /// but does include the predecessor block in the AliveBlocks set (unless that
75 /// block also defines the value). This leads to the (perfectly sensical)
76 /// situation where a value is defined in a block, and the last use is a phi
77 /// node in the successor. In this case, AliveBlocks is empty (the value is
78 /// not live across any blocks) and Kills is empty (phi nodes are not
79 /// included). This is sensical because the value must be live to the end of
80 /// the block, but is not live in any successor blocks.
82 /// AliveBlocks - Set of blocks in which this value is alive completely
83 /// through. This is a bit set which uses the basic block number as an
86 SparseBitVector<> AliveBlocks;
88 /// NumUses - Number of uses of this register across the entire function.
92 /// Kills - List of MachineInstruction's which are the last use of this
93 /// virtual register (kill it) in their basic block.
95 std::vector<MachineInstr*> Kills;
97 VarInfo() : NumUses(0) {}
99 /// removeKill - Delete a kill corresponding to the specified
100 /// machine instruction. Returns true if there was a kill
101 /// corresponding to this instruction, false otherwise.
102 bool removeKill(MachineInstr *MI) {
103 std::vector<MachineInstr*>::iterator
104 I = std::find(Kills.begin(), Kills.end(), MI);
105 if (I == Kills.end())
111 /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
112 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
114 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
115 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
116 /// MBB, it is not considered live in.
117 bool isLiveIn(const MachineBasicBlock &MBB,
119 MachineRegisterInfo &MRI);
125 /// VirtRegInfo - This list is a mapping from virtual register number to
126 /// variable information.
128 IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
130 /// PHIJoins - list of virtual registers that are PHI joins. These registers
131 /// may have multiple definitions, and they require special handling when
132 /// building live intervals.
133 SparseBitVector<> PHIJoins;
135 /// ReservedRegisters - This vector keeps track of which registers
136 /// are reserved register which are not allocatable by the target machine.
137 /// We can not track liveness for values that are in this set.
139 BitVector ReservedRegisters;
141 private: // Intermediate data structures
144 MachineRegisterInfo* MRI;
146 const TargetRegisterInfo *TRI;
148 // PhysRegInfo - Keep track of which instruction was the last def of a
149 // physical register. This is a purely local property, because all physical
150 // register references are presumed dead across basic blocks.
151 MachineInstr **PhysRegDef;
153 // PhysRegInfo - Keep track of which instruction was the last use of a
154 // physical register. This is a purely local property, because all physical
155 // register references are presumed dead across basic blocks.
156 MachineInstr **PhysRegUse;
158 SmallVector<unsigned, 4> *PHIVarInfo;
160 // DistanceMap - Keep track the distance of a MI from the start of the
161 // current basic block.
162 DenseMap<MachineInstr*, unsigned> DistanceMap;
164 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
165 /// uses. Pay special attention to the sub-register uses which may come below
166 /// the last use of the whole register.
167 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
169 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
170 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
171 SmallVector<unsigned, 4> &Defs);
172 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
174 /// FindLastRefOrPartRef - Return the last reference or partial reference of
175 /// the specified register.
176 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
178 /// FindLastPartialDef - Return the last partial def of the specified
179 /// register. Also returns the sub-registers that're defined by the
181 MachineInstr *FindLastPartialDef(unsigned Reg,
182 SmallSet<unsigned,4> &PartDefRegs);
184 /// analyzePHINodes - Gather information about the PHI nodes in here. In
185 /// particular, we want to map the variable information of a virtual
186 /// register which is used in a PHI node. We map that to the BB the vreg
188 void analyzePHINodes(const MachineFunction& Fn);
191 virtual bool runOnMachineFunction(MachineFunction &MF);
193 /// RegisterDefIsDead - Return true if the specified instruction defines the
194 /// specified register, but that definition is dead.
195 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
197 //===--------------------------------------------------------------------===//
198 // API to update live variable information
200 /// replaceKillInstruction - Update register kill info by replacing a kill
201 /// instruction with a new one.
202 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
203 MachineInstr *NewMI);
205 /// addVirtualRegisterKilled - Add information about the fact that the
206 /// specified register is killed after being used by the specified
207 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
209 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
210 bool AddIfNotFound = false) {
211 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
212 getVarInfo(IncomingReg).Kills.push_back(MI);
215 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
216 /// register from the live variable information. Returns true if the
217 /// variable was marked as killed by the specified instruction,
219 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
220 if (!getVarInfo(reg).removeKill(MI))
223 bool Removed = false;
224 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
225 MachineOperand &MO = MI->getOperand(i);
226 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
233 assert(Removed && "Register is not used by this instruction!");
238 /// removeVirtualRegistersKilled - Remove all killed info for the specified
240 void removeVirtualRegistersKilled(MachineInstr *MI);
242 /// addVirtualRegisterDead - Add information about the fact that the specified
243 /// register is dead after being used by the specified instruction. If
244 /// AddIfNotFound is true, add a implicit operand if it's not found.
245 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
246 bool AddIfNotFound = false) {
247 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
248 getVarInfo(IncomingReg).Kills.push_back(MI);
251 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
252 /// register from the live variable information. Returns true if the
253 /// variable was marked dead at the specified instruction, false
255 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
256 if (!getVarInfo(reg).removeKill(MI))
259 bool Removed = false;
260 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
261 MachineOperand &MO = MI->getOperand(i);
262 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
268 assert(Removed && "Register is not defined by this instruction!");
273 void getAnalysisUsage(AnalysisUsage &AU) const;
275 virtual void releaseMemory() {
279 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
281 VarInfo &getVarInfo(unsigned RegIdx);
283 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
284 MachineBasicBlock *BB);
285 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
286 MachineBasicBlock *BB,
287 std::vector<MachineBasicBlock*> &WorkList);
288 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
289 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
292 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
293 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
296 /// isLiveOut - Determine if Reg is live out from MBB, when not considering
297 /// PHI nodes. This means that Reg is either killed by a successor block or
298 /// passed through one.
299 bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
301 /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
302 /// variables that are live out of DomBB and live into SuccBB will be marked
303 /// as passing live through BB. This method assumes that the machine code is
304 /// still in SSA form.
305 void addNewBlock(MachineBasicBlock *BB,
306 MachineBasicBlock *DomBB,
307 MachineBasicBlock *SuccBB);
309 /// isPHIJoin - Return true if Reg is a phi join register.
310 bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
312 /// setPHIJoin - Mark Reg as a phi join register.
313 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
316 } // End llvm namespace