1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/SmallVector.h"
40 class MachineRegisterInfo;
41 class TargetRegisterInfo;
43 class LiveVariables : public MachineFunctionPass {
45 static char ID; // Pass identification, replacement for typeid
46 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {}
48 /// VarInfo - This represents the regions where a virtual register is live in
49 /// the program. We represent this with three different pieces of
50 /// information: the instruction that uniquely defines the value, the set of
51 /// blocks the instruction is live into and live out of, and the set of
52 /// non-phi instructions that are the last users of the value.
54 /// In the common case where a value is defined and killed in the same block,
55 /// There is one killing instruction, and AliveBlocks is empty.
57 /// Otherwise, the value is live out of the block. If the value is live
58 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
59 /// the liveness range ends are not included in AliveBlocks, instead being
60 /// captured by the Kills set. In these blocks, the value is live into the
61 /// block (unless the value is defined and killed in the same block) and lives
62 /// until the specified instruction. Note that there cannot ever be a value
63 /// whose Kills set contains two instructions from the same basic block.
65 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
66 /// value in one of its predecessor blocks, it is not listed in the kills set,
67 /// but does include the predecessor block in the AliveBlocks set (unless that
68 /// block also defines the value). This leads to the (perfectly sensical)
69 /// situation where a value is defined in a block, and the last use is a phi
70 /// node in the successor. In this case, AliveBlocks is empty (the value is
71 /// not live across any blocks) and Kills is empty (phi nodes are not
72 /// included). This is sensical because the value must be live to the end of
73 /// the block, but is not live in any successor blocks.
75 /// AliveBlocks - Set of blocks of which this value is alive completely
76 /// through. This is a bit set which uses the basic block number as an
79 BitVector AliveBlocks;
81 /// UsedBlocks - Set of blocks of which this value is actually used. This
82 /// is a bit set which uses the basic block number as an index.
85 /// NumUses - Number of uses of this register across the entire function.
89 /// Kills - List of MachineInstruction's which are the last use of this
90 /// virtual register (kill it) in their basic block.
92 std::vector<MachineInstr*> Kills;
94 VarInfo() : NumUses(0) {}
96 /// removeKill - Delete a kill corresponding to the specified
97 /// machine instruction. Returns true if there was a kill
98 /// corresponding to this instruction, false otherwise.
99 bool removeKill(MachineInstr *MI) {
100 std::vector<MachineInstr*>::iterator
101 I = std::find(Kills.begin(), Kills.end(), MI);
102 if (I == Kills.end())
112 /// VirtRegInfo - This list is a mapping from virtual register number to
113 /// variable information. FirstVirtualRegister is subtracted from the virtual
114 /// register number before indexing into this list.
116 std::vector<VarInfo> VirtRegInfo;
118 /// ReservedRegisters - This vector keeps track of which registers
119 /// are reserved register which are not allocatable by the target machine.
120 /// We can not track liveness for values that are in this set.
122 BitVector ReservedRegisters;
124 private: // Intermediate data structures
127 MachineRegisterInfo* MRI;
129 const TargetRegisterInfo *TRI;
131 // PhysRegInfo - Keep track of which instruction was the last def of a
132 // physical register. This is a purely local property, because all physical
133 // register references are presumed dead across basic blocks.
134 MachineInstr **PhysRegDef;
136 // PhysRegInfo - Keep track of which instruction was the last use of a
137 // physical register. This is a purely local property, because all physical
138 // register references are presumed dead across basic blocks.
139 MachineInstr **PhysRegUse;
141 SmallVector<unsigned, 4> *PHIVarInfo;
143 // DistanceMap - Keep track the distance of a MI from the start of the
144 // current basic block.
145 DenseMap<MachineInstr*, unsigned> DistanceMap;
147 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
148 /// uses. Pay special attention to the sub-register uses which may come below
149 /// the last use of the whole register.
150 bool HandlePhysRegKill(unsigned Reg);
152 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
153 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
155 /// FindLastPartialDef - Return the last partial def of the specified register.
156 /// Also returns the sub-register that's defined.
157 MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
159 /// hasRegisterUseBelow - Return true if the specified register is used after
160 /// the current instruction and before it's next definition.
161 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
162 MachineBasicBlock *MBB);
164 /// analyzePHINodes - Gather information about the PHI nodes in here. In
165 /// particular, we want to map the variable information of a virtual
166 /// register which is used in a PHI node. We map that to the BB the vreg
168 void analyzePHINodes(const MachineFunction& Fn);
171 virtual bool runOnMachineFunction(MachineFunction &MF);
173 /// RegisterDefIsDead - Return true if the specified instruction defines the
174 /// specified register, but that definition is dead.
175 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
177 //===--------------------------------------------------------------------===//
178 // API to update live variable information
180 /// replaceKillInstruction - Update register kill info by replacing a kill
181 /// instruction with a new one.
182 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
183 MachineInstr *NewMI);
185 /// addVirtualRegisterKilled - Add information about the fact that the
186 /// specified register is killed after being used by the specified
187 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
189 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
190 bool AddIfNotFound = false) {
191 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
192 getVarInfo(IncomingReg).Kills.push_back(MI);
195 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
196 /// register from the live variable information. Returns true if the
197 /// variable was marked as killed by the specified instruction,
199 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
200 if (!getVarInfo(reg).removeKill(MI))
203 bool Removed = false;
204 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
205 MachineOperand &MO = MI->getOperand(i);
206 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
213 assert(Removed && "Register is not used by this instruction!");
217 /// removeVirtualRegistersKilled - Remove all killed info for the specified
219 void removeVirtualRegistersKilled(MachineInstr *MI);
221 /// addVirtualRegisterDead - Add information about the fact that the specified
222 /// register is dead after being used by the specified instruction. If
223 /// AddIfNotFound is true, add a implicit operand if it's not found.
224 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
225 bool AddIfNotFound = false) {
226 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
227 getVarInfo(IncomingReg).Kills.push_back(MI);
230 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
231 /// register from the live variable information. Returns true if the
232 /// variable was marked dead at the specified instruction, false
234 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
235 if (!getVarInfo(reg).removeKill(MI))
238 bool Removed = false;
239 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
240 MachineOperand &MO = MI->getOperand(i);
241 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
247 assert(Removed && "Register is not defined by this instruction!");
251 void getAnalysisUsage(AnalysisUsage &AU) const;
253 virtual void releaseMemory() {
257 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
259 VarInfo &getVarInfo(unsigned RegIdx);
261 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
262 MachineBasicBlock *BB);
263 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
264 MachineBasicBlock *BB,
265 std::vector<MachineBasicBlock*> &WorkList);
266 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
270 } // End llvm namespace